Design Ideas: June 22, 1995
Fixed-point-DSP users are aware of overflow problems that frequently occur in current algorithms such as digital filtering. Many solutions to problems such as floating point or block floating point exist; these methods, however, are cumbersome and slow to execute on fixed-point machines. An alternative is to adopt a mixed-number format consisting of an integer and a fractional part. This technique is particularly attractive for fixed-point processors with wide data words expressed in bits. An example is the 24-bit DSP56001 from Motorola. Fig 1 shows a possible fit and the covered range for such a format.
This representation-with one sign bit, seven bits for the integer part, and 16 bits for the fractional portion-particularly suits DSP algorithms (and receives implicit support from Motorola). Its advantage is straightforward use of the DSP's multiplier. However, the format of the result is unsuitable for further computations (Fig 2).
It's necessary to reformat, but, unlike Analog Devices' ADSP210x or Texas Instruments' DSPs, the DSP56001 doesn't come equipped with a barrel shifter. So, the DSP56001 must execute the program fragment in Listing 1 to reformat. The whole process takes 10 cycles, which isn't negligible in a lengthy loop. The simple hardware fix in Fig 3 speeds this computing situation. After a mixed-format multiplication, you should save the result in a register, from which you can read it suitably reformatted. The program fragment in Listing 2 performs the reformatting in just four cycles.
The circuit count is six IC packages. Because it's essentially a bus circuit, you can implement it as an add-on in existing systems (provided the system is designed to accept extensions). Alternatively, you could configure the circuit using about one-third of a single Xilinx FPGA 2000 or 3000 Series. Using the FPGA, the circuit count is two, because of the required eight-pin Xilinx serial initialization PROM (or some other popular PROM like the 27xxx Series). (DI #1713)