Design Ideas: June 22, 1995
The track-and-hold (T/H) circuit in Fig 1 works well in applications using a low-voltage single supply, such as in battery-powered designs. Despite the low supply voltage, output-signal dynamic range remains high thanks to the rail-to-rail output swing of the amplifiers and switches. S/N ratio is also high because of the wide output-signal range and low amplifier noise. By using a quad JFET op amp and a quad analog switch, the T/H circuit also features low parts count (12 parts total) and small board real estate (with SOICs, <3/4> in.During track mode, S1 and S4 are closed, and S2 is open. The circuit transfer function is thus VOUT-2VIN. S1 and S4 open, and S2 closes for hold mode. The hold-mode output remains constant at the output voltage that immediately preceded the hold command. During the transition from track to hold mode, S4 reduces the pedestal, or hold-step, error by injecting the same amount of charge (typically 11 pC) into the noninverting input of IC1C that S1 injects into the inverting input. This equal injection creates a common-mode voltage that IC1C rejects by the amount of its CMRR. Pedestal error for this circuit is less than 3 mV over the entire 0 to 3.3V input range. Increasing CH and C1 reduces pedestal error further-but at the expense of increased acquisition time.
As a result of S1 feedthrough, an attenuated and undesired input signal appears at the inverted input of IC1C during hold mode. S3 remains open in both modes and allows feedthrough of the input signal to the noninverting input of IC1C. Because S1 and S3 exhibit similar feedthrough characteristics, the common-mode rejection of IC1C reduces signal feedthrough by more than 60 dB. Inverting-amplifier configurations in single-supply applications require a false-ground reference. In this circuit, R1 and R2 divide the supply voltage symmetrically, and IC1A buffers the voltage and thus creates a low-impedance false-ground reference for the T/H circuit.
Hold-mode droop rate is proportional to parasitic current. Quad JFET op amps are well-suited for T/H circuits because of their low input-bias-current specifications (typically 3 pA for the AD824). By using JFET op amps and low-leakage (<100 pA) CMOS switches, this design keeps droop lower than 20 mV/sec. Higher values of CH produce lower droop rates. CH and C1 should be polystyrene, polypropylene, or Teflon capacitors, because these types exhibit low leakage and dielectric absorption. The design uses metal-film resistors of 1% tolerance. Finally, using the ADG513 CMOS switch simplifies the switch-control circuitry to only one line, because this device has two normally open and two normally closed switches. (DI #1717)