ASIC oscillator cells reduce system timing costs

Marvin A Veeser,
Raltron Electronics Corp

Few electronic products can get by without a sense of timing. A stable frequency source is critical for a range of applications, from generating or detecting radio frequencies to internal logic clocking. Quartz crystals help generate the frequency, but you need active electronics to sustain oscillations to drive an output load.

Traditionally, quartz-crystal oscillators have been self-contained in hybrid oscillator packages or are designed in-house using inverters and stand-alone crystal units. Hybrid oscillators can be costly, and in-house designs can eat up a lot of board space, even if you use SMT (surface-mount-technology) parts.

PICTURE 1

This section of a field-programmable gate array (a) shows the on-chip electronics for a crystal-driven system-clock oscillator. Suggested external component values (b) are as follows: R₁=0.5 to 1 M[uom], R₂=0 to 1 k[uom], C₁ and C₂=10 to 40 pF, and Y₁=1 to 20 MHz, AT-cut, parallel-resonant. The device shown is a Xilinx XC3020 housed in a 68-pin PLCC. (Courtesy Xilinx Inc)

But the increasing de-mand for new, smaller products, such as disk drives and PCMCIA boards, has prompted ASIC manufacturers to provide all the electronics you need on-chip in standard cells. All you do is select either an AT or a BT cut, a parallel-resonant quartz crystal, and up to four passive parts.

In the field-programmable gate-array (FPGA) example in Fig 1a, the highlighted area in the lower right corner of the die shows the location of a high-speed inverting amplifier and an auxiliary buffer. When the FPGA is configured at runtime, the oscillator connects to the external crystal unit and glue parts first (Fig 1b).

On-chip FPGA programming activates the oscillator circuit early in the configuration process, but the internal clock connection is held off until after the ASIC has completed its configuration. This move gives the oscillator time to stabilize. Stabilized accuracy for quartz crystals in ASIC logic systems is ñ50 ppm.

PICTURE 2

For this version of the commonly used Pierce oscillator, you choose phase-shifting elements C₁ and C₂; to adjust the output impedance, you also choose R_X.

Fig 2 shows the generic form of a Pierce oscillator for quartz crystals. You choose the external phase-shifting elements, C₁ and C₂. You also choose R_X to adjust the output impedance, Z_O. Even though R_X may wind up being 0ê (a short), you should always provide for it to avoid potential layout problems.

Fig 3 shows four combinations of reactances that can occur with an unloaded tank circuit. To determine if and at what frequencies these combinations oscillate, you write the circuit node equations. Oscillation will occur at the frequency for which the reactive term equals zero. For the Pierce oscillator of Case 1 in Fig 3a, oscillation occurs when

R_INm/(ê2C₁C₂),

and the frequency is given by

ê=[sqrt]L₃C₁C/(C₁+C₂)-1.

For Case 1, connecting a crystal at Z₃ satisfies the requirements for oscillation at slightly above the indicated 15-MHz fundamental and 45-MHz overtone frequency, because the crystal appears inductive at those points (Fig 3b). Note that, over most of the frequency spectrum, the crystal appears capacitive, preventing oscillation.

PICTURE 3

Four combinations of reactances can occur with an unloaded tank circuit (a). Case 1 oscillates if Z₃ is inductive; cases 2 and 3 do not oscillate, and case 4 oscillates if Z₃ is capacitive. Case 1 is an example of the Pierce configuration. Over most of the frequency spectrum (b), the crystal appears capacitive, and, thus, can oscillate only near the indicated fundamental and harmonic frequencies.

For correct impedance matching, be aware that oscillator circuits depend on fast rate-of-phase change to govern stability. Perturbations that result from moisture, component variations, and foreign objects in proximity to the oscillator can cause dramatic rates-of-phase change.

During a perturbation, the oscillator cannot satisfy Barkhausen's phase criteria (see box, "ASIC-cell-oscillator basics") at the old frequency, so it changes phase until oscillations can occur. For instance, if a perturbation causes the oscillator to shift 2ø, effecting a change in output frequency of 6 Hz, it would make the phase slope equal to 2/6 or 0.333ø/Hz. You want to try for a much steeper slope--perhaps 40ø/Hz--and should strive for a large impedance mismatch to maximize the phase slope.

In Fig 4, a small C₂ at the output of a low Z_O ASIC does nothing. But if R_X is added such that R_X=XC₂, a +45ø phase shift occurs at the crystal; this phase shift is consistent with design goals. The crux of this exercise is selecting the C₂ value with respect to the ASIC's output impedance.

If R_X is a short, R_OUT is directly in parallel with C₂. The Q of the output-matching network is defined as

Q=(R_OUT+R_X)/XC₂.

Textbooks call for Q=10. Consider compromising, and set Q=2. If the circuit is operating at 40 MHz and the cell has an output impedance of 200ê, C₂ should be 39 pF.

Using the Thevenin equivalent of the output driver (Fig 4c), you can see that the phase shift at the output-C₂ junction is a function of the value of C₂. Using the Norton equivalent (Fig 4d), you can see that the output impedance is directly across C₂. Therefore, if Q<2, increase R_X (or C₂). Strive to design the circuit for 2 less than Q less than 5.

• ASIC drive capability
  Consider ASIC drive capability when selecting components. Capacitor C₂'s current (i) equals dQ/dt. Therefore, Q equals the integral of idt, and the voltage is the integral of idt/C. The ASIC driver must be capable of charging C₂ quickly. If C₂ is small, it can charge rapidly. If it's large, and the ASIC driver has limited transconductance (g_m), C₂ will not charge significantly, and the voltage developed across C₂ will be limited.
  The output signal from the ASIC cell drives C₂ as well as the internal logic elements that produce the system clock. If this signal is small in amplitude, it could be cause for concern--logic levels at the ASIC output should switch fully from 20 to 80% of supply voltage.
  You can increase signal level two ways: Either reduce the load (C₂ capacitance) or increase the value of R_X. If the value of R_X is equal to XC₂, the signal at the crystal will be one-half the signal going to the system clock.
  Increasing R_X reduces crystal drive level, reduces EMI, and increases rate-of-phase change, all of which result in a clocking system of greater stability and higher reliability. (Be sure to measure signals only with a nonloading FET scope probe, such as the Tektronix Model P6204. Do not use an ordinary 10-pF passive probe, which will load the circuit.)
  Strive for a large signal on the ASIC output--at least 4V p-p for 5V logic. Increasing the value of R_X increases the output level until the point at which crystal losses cannot be made up (then signal level begins to fall off).
  Now, consider the voltage gain from output to input. The voltage feeding back from output to input through the passive elements may be smaller or larger than the signal at the output. It may seem strange that a signal can be increased by way of passive elements. However, if the gate input has high resistance, the output signal is charging a tap on an L-C tank circuit, and the passive gain is roughly V_IN/V_OUT=C₂/C₁.
  To verify this passive gain, place a FET scope probe on the input of the cell at C₁; then, remove C₁. Observe that the signal increases until the electrostatic-discharge protection diodes clamp the signal. Therefore, to ensure an output-to-input voltage gain sufficient to make up signal losses through the crystal, select C₂ to be between 1.1 and 1.5 times C₁.
  The feedback resistor of Fig 2 biases the input of the inverter to make the inverter operate as a Class A amplifier. The resistor's value should be high enough to prevent loading of the feedback network and allow the inverter to operate in the center of its linear range.
  For fundamental-mode and overtone oscillators with tank circuits, the feedback resistor should be 0.5 to 1.0 Mê at 20 MHz and up and 1.0 to 5.0 Mê below 20 MHz.
  

• Selecting a crystal

  Oscillator design for clocking must be simple, inexpensive, and reliable. The basic AT and BT cuts invented in 1934 are still the cuts of choice. AT cuts are used in both fundamental and overtone modes; BT cuts are used in the fundamental mode only. AT-cut resonators' frequency-vs-temperature curves (Fig A) follow a third-order curvature with a zero-crossing inflection point at 25øC. Standard frequency-vs-temperature specs are ñ50 ppm from 20 to +70øC; stability limits are ñ10 ppm for the same temperature range. PICTURE 1 AT-cut crystals' frequency-vs-temperature characteristic follows a third-order curvature with a zero-crossing inflection point at 25[deg]C. BT-cut crystals' characteristic follows a parabola with a maximum that is nearly room temperature. BT-cut resonators' curves follow a parabolic curve with the maximum frequency nearly room temperature. The frequency decreases at both higher and lower temperatures. AT-fundamental strip crystals are inexpensive and are commonly used for frequencies ranging from 3.5 to 40 MHz. The crystal's design specifies that the plate's thickness in mils be equal to 66.4 divided by the frequency in megahertz. Strip crystals are troubled with flexure- and face-shear coupling that must be accounted for in the width-to-thickness design ratio. Moreover, process-design limits restrict the upper and lower frequency limits. At the low end of the spectrum, thickness is almost 0.020 in. and requires special processing, such as unidirectional contouring and edge tilting. At 40 MHz, the AT strip crystal is only 0.00166 in. thick and must be handled with vacuum picks. In designing overtone strip crystals, coupling restricts the upper frequency limits to about 70 MHz. In addition to having the flexure- and face-shear coupling modes common in fundamental crystals, there are also couplings to inharmonic (not harmonically related to the main mode) overtones of both Z- and X-thickness-shear modes. Overtone design of strip resonators is more complicated than fundamental-mode design; tighter tolerance requirements for repeatable device performances are normal. BT fundamental strip crystals are lower in cost than AT strip crystals and are 1.521 times thicker. The thicker resonator reduces the cost of processing. Many strip-crystal units in the 30- to 45-MHz range are fundamental BT plates. Inverted mesa crystals use an etching technique to produce bilevel resonators. The thicker, lapped portion is used for mounting support. The thinner, etched portion contains the electrode. Fundamental crystals are available from 60 to 120 MHz, and third overtones are available to 350 MHz. Fig B shows three common circuits you can employ with AT- or BT-cut crystals in fundamental or overtone modes. PICTURE 2 These circuits derive usable frequency outputs from crystals. Circuit (a) serves in fundamental-mode operation of both AT- and BT-cut crystals. Circuit (b) is the preferred choice for overtone operation of AT-cut crystals, but you can use (c) at the highest overtone frequencies or if the driver transconductance is limited.

PICTURE 4

• The crux of good ASIC oscillator design is to select the proper value of C₂ with respect to the ASIC's output impedance, Z_O. For an ASIC cell with external R_X (a), you can derive an input equivalent circuit (b), and you can derive output Thevenin (c) and Norton (d) equivalent circuits.
  

• Crystal specifications
  Low-resistance crystals are desirable for better stability and reliability, but they're more costly than high-resistance parts. For parallel-resonating crystals, the effective series resistance (ESR) should be specified as
  ESR=R_M(1+C_O/C_L)2,
  where R_M is motional resistance, C_O is static capacitance, and C_L is load capacitance. Specify the crystal's resistance as low as possible for the price.
  Load capacitance is specified as the amount of capacitance placed in parallel with a crystal's leads that will cause the oscillator to operate. Stray capacitance around the host pc board and the ASIC input/output capacitance also contributes to the load.
  In Fig 2, C₁ and C₂ are in series with each other. Proper selection of C₁ and C₂ requires that stray capacitance be considered for all calculations. Typical ASIC oscillators have roughly 10 pF of stray capacitance on both the input and output.
  For the first design iteration, calculate the load capacitance with no consideration for stray and input or output capacitance. Next, add 4 to 7 pF to C_L to account for stray, C_IN, and C_OUT capacitance values as follows:
  C_L=C₁C₂/(C₁+C₂)+5 pF.
  

• Test with ramp and step
  Testing should be done on a breadboard that simulates the final product. Application of starting voltage should include both ramp and step functions.
  During power-supply ramp testing of overtones, you can expect that operation will be at the fundamental frequency until the supply reaches about 2.5V (for a 5V design). Corrections for lower mode starting are often done by decreasing the value of C₂ in Fig 2.
  Power-supply step-function testing of fundamental and overtone designs requires instantaneous power applications. This testing should include all voltages up to the ASIC's absolute maximum, usually about 7V. During step-function testing at high voltage, the oscillator may try to jump to the next higher oscillating mode, which can usually be corrected by increasing the value of C₂.
  
  

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• Author's biography
  PICTURE
  Marvin A Veeser is engineering manager at Raltron Electronics Corp (Miami), where he has worked for two years developing a variety of crystal oscillators. He holds a BS degree from Northern Illinois University, DeKalb, IL.
  

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