Design Ideas: August 3, 1995
Daniel Segarra,
The circuit in Fig 1 loads 4 address
bits and 8 data bits into IC8's 8-bit octal, two-quadrant
multiplying DAC from a PC parallel port. Initially, the circuit
loads the desired data on the D0 through D7
pins of the parallel port into shift register IC1 when
the parallel port's STR pin goes low. Next, the circuit loads
the desired address from the port's D0 through D3
pins into register IC2 when the port's ALF pin goes
low.
The data shift from the registers into the DAC when the INI pin (CTRLO) of the parallel port goes high. The circuit formed by IC3 and IC4A synchronizes INI with the on-card clock. IC6B performs an inversion and generates a pulse at LOADL, which goes low for the duration of one clock period each time INI goes high. LOADL is synchronous with the on-card clock signal, CLK. The LOADL signal loads binary 1 into counter IC7 and simultaneously drives the clock-inhibit pins of shift registers IC1 and IC2 low via IC6A. This action puts the registers in serial-out mode.
IC5's oscillator and the remaining gates of IC4 produce three clock signals: CLK, CLKN, and GCLK. CLK and CLKN are out of phase, and GCLK is a gated clock in phase with CLK. Data shift out of the registers on the rising edge of CLKN and shift into the DAC on the rising edge of CLK. Initially, the first of four leading zeros appears at the SO pin of IC2. A total of 15 CLKN edges are necessary to shift out the remaining zeros followed by A3 through A0 and D7 through D0, in that order. During this time, IC7 counts from its loaded state of binary 1 to 15.
Note that the counter can't begin counting until the LOADL signal goes high. Thus, the DAC misses the first two leading zeros. The DAC's internal register simply shifts out the last two leading zeros by the time the 14th rising edge of CLK occurs. This edge also produces the DACLD signal—the counter's ripple carry out—that disables GCLK, strobes the load pin of the DAC, and causes the inhibit pin of the shift registers to go high. The cycle is now complete, and the circuit can load new address and data bits from the parallel port.
The program in Listing 1 accepts an address (1 through 8) and data (0 through 255) in decimal format and sends the information to the DAC. Addresses 1 through 8 correspond to converters A through H, respectively. The output is as follows: VOUT=(data/128)x1.5V. We found that, for the IBM PC/XT, the LPT1 port address was 3BCH (Data Register 3BCH and control register 3BEH). You can download the listing from EDN BBS /DI_SIG #1738.