Systems for telecommunications, real-time transaction processing, and fault-tolerant computing must stay on-line during maintenance. For designers of such systems, the ability to perform live insertion and removal of boards has always been a desirable feature. More recently, the availability of open-architecture computing equipment, removable disk drives, and user-accessible backplanes and PC Cards has increased designers' needs for live-insertion/removable-capable devices.

Removing power from a module or board but leaving active signals connected to a bus or backplane causes a situation with fault conditions virtually identical to those of live insertion/removal. The difference is that, unlike live insertion/removal, your motive is to reduce system power consumption by idling unneeded subsections of the system. If the board or module contains CMOS drivers at its periphery, however, you achieve little in power savings. Standard CMOS devices with inputs or outputs tied to the bus attempt to power up and operate on this unintended supply, provided through their input-protection or drain-isolation junctions. Instead of benefiting from reduced power consumption, the subsystem may suffer data corruption, device damage, or circuit-board failure due to the large current flow this phantom-power condition causes.

You can divide live-insertion devices into classifications A, AA, and B (see box, "How tolerant are you?"). Each provides varying degrees of the following capabilities:

Data retention means that when you reduce the supply to a level below the guaranteed operating range and then return it to the allowed range, all internal storage elements and outputs retain or return to the values they had before the supply reduction. If the IC is to retain valid data, input, output, and I/O switching cannot occur during supply reduction or restoration.

Also, consider IC behavior during the various power-rail states. Power-down, high-impedance devices have inputs and outputs that present no dc load to applied external signals, even when the devices' supply voltage is nearly zero. Power-down high impedance is a requirement for Classification A devices.

Power-up reset means that the device's latches and outputs are guaranteed to be at valid and predetermined logic levels following application or reapplication of the supply rail. In a three-state power-up device, the outputs remain in a high-impedance condition during supply ramping and unconditionally return to the high-impedance condition when the supply drops below the power-up threshold. The IC's design prevents the outputs from becoming active until the supply rises to a predetermined threshold level. This situation, in turn, prevents the IC from presenting invalid data at its outputs. In addition, inputs are internally conditioned via bus hold or externally driven via pull-up resistors to the ramping supply.

Input-bus-hold hysteresis lacks the usual buffering between the feedback-device output and the input pin. The purpose of bus hold is to establish a valid, or safe, input level on otherwise-floating inputs. More circuit designers are trying to use the bus-hold output-low or output-high current to act as the termination supply, but bus hold does not suit this application.

Although most circuit designers don't worry about the details of internal IC circuitry and topology, an effective design for live-insertion/removal requires that you understand how these structures affect what you can expect.

Standard CMOS-logic devices, including the CD4000, HC/HCT, ACT, and LV families, fit the live-insertion/removal-intolerant definition. These devices use complementary input-protection junctions to provide ESD immunity (Fig 1a). The input-to-V_DD P+/N clamping diode, D₁, creates a live-insertion/removal obstacle because it becomes forward-biased whenever you apply a positive-going signal to an input if you do not apply V_DD. This scenario assumes that a floating V_DD node discharges nearly to ground potential. This approach results in a low-impedance path from the input node to V_DD and subsequent failures of input leakage current.

Live insertion/removal causes forward, or avalanche, junction currents. These currents develop potential differences in the substrate and local wells of the device as charge escapes to the supplies. This scenario differs from that of well-controlled channel and drift currents that are inherent with conventionally operated MOS devices. In an N starting-material CMOS process, the P well forms the base of a relatively high-performance parasitic vertical npn, and the substrate represents the base of the lateral pnp. In this process, any local potential differences in the N substrate or P well inadvertently provide the forward voltage to turn on these parasitic bipolars. SCR triggering or latch-up may result.

For the output circuit of a standard CMOS logic device, you typically use a large PMOS pull-up transistor to provide large, high-level output current and large noise margin. (Fig 1b). The drain-isolation P+/N junction inherent to these PMOS transistors must remain reverse-biased to preserve proper device operation. Unfortunately, you forward-bias this junction if you apply any signal >V_DD to the output when V_DD is [Greek];0V or any signal >V_DD+ the forward drop across the diode.

As a result of these high-current conditions, the device may have behavior ranging from a subtle shift in dc characteristics to compromised reliability, which is unapparent at the time of the stress, through catastrophic failure. You may see outputs do one or more of the following: glitch low-high-low as V_DD rises, remain low, glitch low-high and then collapse to and track V_DD as it rises, glitch low-high and oscillate, or fail outright.

Unfortunately, you can't predict or reliably repeat the live-insertion/removal behavior for a device or for a class of devices. The actual behavior depends on factors such as dc-junction leakage, parasitic capacitance, and other environmental conditions, such as the presence of external electric and magnetic fields and supply and ground noise.

Input overvoltage-tolerant CMOS devices, including VHC, LVX, LVC, and FCT types, have no P+/N junctions between their input node and V_DD. (LVC's inclusion in this group is questionable because its data sheets specify an absolute maximum high-level input voltage level of 4.6V, so that you cannot apply 5V signals to LVC inputs.) The lack of these junctions lets you apply input signals containing voltage components >V_DD. When V_DD is -0V, which is the case just before live insertion/removal, any positive-going signal that you apply to the input contains components >V_DD.

The input overvoltage tolerance of these devices is due to the lack of an upper diode in their input structure (Fig 2). These devices have Classification B live-insertion/removal performance. Unfortunately, this classification often comes at the expense of compromised positive-ESD immunity. The ESD block in Fig 2 represents the alternate positive-discharge-protection element. This alternate circuit does not include a forward path to V_DD but instead routes positive discharges to ground. To implement the alternate-ESD scheme, logic vendors use different circuitry, including reach-through NMOS transistors, gateless NMOS, field-threshold NMOS, grounded-gate NMOS, zener diode, floating-base npn, and others.

The common feature among this group is the absence of a forward path from the input node to V_DD. From a live insertion/removal point of view, the output circuits in this class are identical to the standard complementary MOS output circuit in Fig 2.

Tristated output overvoltage-tolerant CMOS/BiCMOS, a relatively new class of CMOS or mostly CMOS logic, includes LCX and LVT devices. These devices have inputs and outputs that present a high-impedance load to the host system at both the devices' inputs and outputs when V_DD is not applied. In addition to the alternate input structure, these devices feature novel CMOS output circuitry that tolerates the application of output voltages >V_DD, with V_DD; 0V or an output in tristate mode, without substantially increasing high-level, high-impedance leakage current. Product lines fitting this description include the Motorola/National/ Toshiba LCX low-voltage family and the Texas Instruments LVT low-voltage BiCMOS logic. These products offer Classification A live-insertion/removal tolerance.

In an overvoltage-tolerant input circuit (Fig 3), P₁ and N₁ provide hysteresis by routing feedback directly to the input node. This technique contrasts to the usual technique, in which you apply the feedback one stage further into the buffer to avoid back-driving the bus. In this approach, directly charging the input is desirable because it establishes a valid level to the input inverter, P₂ and N₂, when the bus is floating or otherwise indeterminate. Reverse-biased Schottky barrier diode S₁ prevents the corruption of the 3V supply in the event that the input charges above the static V_DD level. Without S₁, the drain-bulk P+/N junction of P₁, would be forward-biased when V_IN rises above V_DD plus the forward diode drop at P₁.

In an overvoltage-tolerant output circuit (Fig 4), analog multiplexer X₁ passes on the larger of V_DD or V_O. These devices thus isolate V_O from V_DD and tolerate overvoltage conditions. When V_DD is -0, these devices treat any signal greater than that at the output as an overvoltage condition.

CMOS/BiCMOS with power-up/ down, high-impedance devices relates closely to the overvoltage-tolerant families but includes circuitry (the components with * in Fig 4) to prevent outputs from activating whenever V_DD is below a predetermined level. These Classification AA live-insertion/removal products include ABT and LVTZ devices.

This extra circuitry prevents invalid or electrically unusable signals that develop during the supply-settling time from presenting to the host bus or other inputs. The extra logic in the output predriver overrides the enable signals that are otherwise delivered to complementary output pairs as long as diodes D₁ and D₂ remain reverse-biased. This approach effectively holds the outputs in the high-impedance condition until V_DD rises to a level equal to or greater than twice the forward voltage of D₁.

Analog NMOS switches can be implemented without P+/N junctions between any pins and V_DD (Fig 5); examples include Quality Semiconductor's QuickSwitch series, Texas Instruments' CBT family, and National Semiconductor's BusSwitches. These devices generally offer the same live-insertion/removal capabilities as LVT and LCX devices. The critical live-insertion/removal constraint with these devices is that the input levels--or control inputs in the case of the NMOS switches--must remain at valid levels during supply power-up. You can most easily accomplish this goal by using active termination or input pull-up resistors.

The ESD block in Fig 5 represents the alternate positive-ESD element. Similar to that of Fig 2, this protection circuit does not include a forward path to V_DD; instead, it routes positive discharges to ground. These devices meet the re-quirements for Classification A live-in-sertion/removal tolerance.

Extended TTL (ETL) technology is a VME-compliant, high-drive logic family featuring overvoltage-tolerant inputs and outputs and additional functionality to improve live insertion/removal support. A "connect-first" pin, V_{DD BIAS}, precharges the host-side outputs to 1.5V to minimize the disturbance of sudden charging or discharging of the inserted ETL pins. As with LCX and LVT devices, you must hold the control inputs at valid levels during supply power-up. You can most easily achieve this goal with active termination or input pull-up resistors. ETL fits the description for Classification A live-insertion/removal performance.

Bus standards, such as the VME64 ETL specification, include specifications for the mechanical keying of modules or subsystems for insertion into live systems. By arranging the order in which you apply power-supply connections, signal connections, and precharge connections to a live-inserted component or subsystem, you avoid certain fault conditions. You can circumvent the problem of temporarily forward-biasing input-protection diodes or PMOS drain-isolation junctions by extending the supply connectors so that they make contact with the backplane before any signal lines do.

You can't make pure CMOS devices unconditionally live-insertable/removable solely by implementing supply/signal sequencing. Keying does eliminate the undesirable forward-biasing of the P+/N input-protection diode and drain-isolation junction inherent to the output PMOS transistor. However, power-up of a CMOS-logic device without establishing valid input levels frequently results in a potentially destructive, high-current condition due to high-frequency oscillation, along with simultaneous conduction through the input complementary pair. Several unpredictable external and internal factors determine whether "hazardous" input levels exist at an otherwise-floating input during live insertion/removal. These factors include

• the voltage that the floating input reaches, due to the divider formed by the ratio of input P+/N junction leakage to V_DD and N+/P leakage to ground
• the presence of terminating networks or pull-up resistors on the input nodes
• the input capacitor's precharged condition
• the static-charge buildup on the subsystem or host
• the ratio of subsystem input leakage to host stray capacitance
• the presence of radiated electromagnetic energy.

You can eliminate the hazards associated with indeterminate inputs when power is applied by using ICs with internal circuitry that sets otherwise-floating inputs to valid levels as soon as power and ground references are available. Two product families featuring circuitry to perform this function--National Semiconductor's dual-supply LVX4245 (B-port only) and Texas Instruments' LVT low-voltage BiCMOS logic family--apply hysteresis directly to the input node, such that under no- or light-load conditions, the input charges or discharges to a valid input level.

Use pull-up resistors to set floating LCX or LVT control input pins to valid levels and avoid problems with outputs leaving tristate mode before you establish proper predriver levels.

By combining careful circuit design with classification A or AA logic, you can develop an acceptably robust and reliable live-insertion/removal subsystem or module. If your application is cost-sensitive at the component level but has extra board space, you have to accommodate live-insertion/removal at the system-design level. By using external, active- or ac-termination schemes, you can use lower cost, less sophisticated standard logic devices without compromising live-insertion/removal requirements. In contrast, for applications where space savings is critical, look at the advanced logic families that feature built-in live-insertion/removal enhancements. Most applications require some external circuitry to allow unconditional live insertion/removal of subsystems.