Design Feature: September 1, 1995

Fig 1 shows an interface circuit you can use for high-speed D/A conversion, using the serial port in the 50-MHz TMS320C25-50 DSP chip. An AD7568 12-bit DAC provides eight output channels and a serial input. You can interface the serial input to the TMS320C25 with a minimal amount of additional logic circuitry. The AD7568 provides great flexibility because it can work from one 5V supply, and it provides four-quadrant multiplication. If you need more than four outputs, the device also has an external address pin to allow addressing more than one DAC.

You can generate the serial clock by dividing the µP's 50-MHz clock by 8, using a counter such as a 74AS161. Thus, the circuit can clock the serial data at a 6.25-MHz rate, which is below the DSP chip's maximum serial-clock rate of 6.7 MHz. The additional logic required is an inverter, a D-type latch, and a 3-to-8 decoder. You need the inverter and latch to transform the TMS320C25's frame-synchronization transfer, FSX, into the proper active-low FSIN signal the DAC requires (Fig 2). The 3-to-8 decoder serves to clear the latch and reset the DAC.

You program the DSP chip's serial port to transfer 16 bits by setting FO to 0. The conversion begins with the falling edge of FSIN. The 12 MSBs (DB15 to DB4) of the bit stream contain the data to be converted. The DB3 bit is an address pin that must match the logic state of the A0 pin. The three LSBs (DB2 to DB0) select one of the eight analog channels to be updated. After the data word is properly formatted, the bit stream transfers to the DAC when you write the data to the TMS320C25's data-transmit register. You can then activate the LDAC pin to update the analog outputs. (The AD7568 also has a simultaneous-update capability.) Fig 3 is the flowchart for the complete D/A-conversion sequence.