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Design Feature: September 1, 1995

Watchdog time-out is independent of reset

Larry Buyan,
Criticare Systems Inc, Waukesha, WI


Many embedded systems use µP supervisors with on-chip watchdog timers. Some supervisors, such as the MAX691, allow you to select different watchdog and reset time-out periods, depending on how you connect pin 7 (Osc In) and pin 8 (Osc Sel). Table 1 in the MAX691 data sheet indicates the available watchdog and reset time-out choices. However, when you implement an extra-long watchdog time-out period by connecting a capacitor from pin 7 to ground and grounding pin 8, the reset time-out increases proportionally. In some embedded-system designs, such as a PC-compatible system with an LCD panel and a BIOS chip that takes a few seconds to initialize, the extended reset time can be undesirable. The circuit in Fig 1 allows you to set the watchdog time-out period independ-ently of reset time-out.

To maintain a short (200-msec) reset time-out and a long (18-sec) watchdog time-out, connect a 330-pF capacitor from pin 7 to ground and a FET (Q1) from pin 8 to ground. Initially, RST is low, Q1 is off, and pin 8 is floating. Approximately 200 msec after 5V is present at pin 3, RST goes high, grounding pin 8. If a 0-to-5V or 5-to-0V transition does not occur within approximately 18 seconds after reset, the cycle repeats. The watchdog time-out period is different during normal operation and immediately after reset (see Table 1).

Table 1—Reset and watchdog time-out selections
Osc sel Osc in Watchdog time-out period Reset time-out period
Normal Immediately after reset
Low External clock input 1024 clks 4096 clks 1024 clks
Low External capacitor (600/47 pF×C) msec (2.4/47 pF×C) msec (800/47 pF×C) msec
Floating Low 100 msec 1.6 sec 200 msec
Floating Floating 1.6 sec 1.6 sec 200 msec




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