Design Feature: September 14, 1995

EDN's 22nd Annual µP/µC Directory - 8-bit chips

Table 1 — EDN µP/µC Directory: 8-Bit Chips

Intel 8051/52

The 8051/52 is an accumulator-based design. The CPU has four banks of eight 8-bit registers in on-chip RAM that are used for context switching. These registers are located within the 8051/52's lower 128 bytes of RAM along with a bit-operation area and scratch-pad RAM. These lower bytes can be addressed directly or indirectly using an 8-bit value. The upper 128 bytes of on-chip data RAM encompass two overlapping address spaces. One space is for directly addressed special-function registers (SFRs); the other space is for indirectly addressed RAM or stack. The SFRs define peripheral operations and configurations. The 8051/52 also has 16 bytes of on-chip RAM that are bit-addressable and are used for flags or variables.

Register indirection uses an 8-bit register for an on-chip RAM address; an off-chip address needs a 16-bit pointer register (DPTR). The 8051/52 has only one DPTR (except for Dallas and Siemens µCs, which have two DPTRs). The DPTR cannot be indexed; however, you can increment the 16-bit DPTR. Program memory accesses can be indexed using MOVC instructions for lookup tables or constants. The CPU has bidirectional and individually addressable I/O lines.

Power management: The CPU has idle and powerdown modes: Idle discontinues CPU processing but leaves the clock, timer, serial-peripheral interface, and serial-communications interface systems enabled. Powerdown stops the clock and all internal processing. Both modes maintain RAM and enable interrupts to wake the CPU. Most peripherals are programmable and can be turned off selectively. Dallas and Siemens devices also provide programmable clock divisors.

Special instructions: The 8051/52 performs extensive bit manipulation via instructions such as set, clear, complement, and jump-on-bit-set or jump-on-bit-clear, only for a 16-byte area of RAM and the SFRs. It can also AND or OR bits with carry bit. Dallas versions have variable-length MOVX. Math functions include add, subtract, increment, decrement, multiply, divide, complement, rotate, and swap nibbles. Some of the Siemens devices have a hardware multiplier/divider for 16-bit multiply and 32-bit divide.

Intel MCS 251

The MCS 251 core is a register-based architecture that is binary-code-compatible with the 8051. The CPU consists of an 8-bit ALU, instruction sequencer, 24-bit PC, and a 40-byte register file, in addition to the four banks of eight registers found on the 8051 architecture. A three-stage pipeline allows the CPU to run at a minimum of two clocks per instruction cycle (versus 12 clocks for the 8051 or four clocks for the Dallas version). The register file can be addressed as bytes, word, or double words, and all registers are available as register pointers (as opposed to the single data pointer of the 8051).

The MCS 251 has an internal 16-bit-wide instruction bus capable of supporting a 16-bit fetch per cycle from the internal code memory through the CPU's bus-interface unit. The data bus is 8 bits wide. To handle large applications, the MCS 251 architecture can perform 24-bit linear addressing for up to a 16-Mbyte memory space (note that specific implementations may vary).

Power management: The MCS 251 has two power-saving modes: idle and powerdown. Idle discontinues CPU processing but leaves the clock, timer, serial-peripheral interface (SPI), and serial-communications interface (SCI) systems enabled. Powerdown stops the clock and all internal processing. Both modes maintain RAM and enable an interrupt to wake the CPU. Most peripherals are programmable and can be turned off selectively.

Special instructions: The MCS 251 has new instructions, in addition to the instructions the 8051 supports. New instructions include 16- and 32-bit arithmetic and logic instructions, conditional jumps, and a jump to the location depending on the result from previous instruction.

Microchip PIC 16Cxx/17Cxx

Register-based PICs comprise three families of controllers: the baseline PIC16C5x, the midrange PIC16Cxx, and the high-end PIC17Cxx. These controllers employ a modified Harvard architecture that supports various instruction word widths. The data paths are 8 bits wide, but the instruction widths are 12, 14, and 16 bits wide for the PIC16C5x, PIC16Cxx, and PIC17Cxx, respectively. This variable-instruction bus width allows most instructions to be held and fetched in a single word and executed in a single pipelined cycle.

The PIC16Cxx lacks provisions for external memory. The PIC17Cxx has a multiplexed external bus--16-bit address and 8-bit data. Multiple register sets make for fast context switching. Interrupts are handled via polling on the PIC16C5x because it lacks interrupt support; the PIC16Cxx and PIC17Cxx devices have eight and 11 interrupt sources, respectively.

Power management: Low-power sleep mode reduces power consumption to only transistor leakage. In this mode, RAM/register contents are maintained.

Special instructions: PIC16/17 bit-manipulation instructions are bit set, clear, test, and bit toggle (only the PIC17Cxx). Math functions include add, subtract, increment, and decrement. Table instructions move data held in program memory--typically constants--to registers for processing. Compare and skip instructions (PIC17Cxx) save code. The PIC16Cxx has a decrement-and-skip-on-0 instruction.

Mitsubishi 37400/WDC 6502

Although the Mitsubishi 37400 is a complete redesign of the 6502, the two architectures have many similarities. The accumulator-based 6502 and 37400 have an 8-bit accumulator and two 8-bit index registers. The stack pointer is 8 bits wide; the PC is 16 bits wide. The CPU is semipipelined--it fetches the next instruction while decoding and executing the current instruction. In conjunction with a relatively fast memory interface, this feature lets code use part of internal RAM as a large register set to hold dynamic variables.

The 6502 and 37400 have a 64-kbyte unified address space, which divides into 256-byte pages for X, Y indexing. The 0 page is the first page in memory and is easily addressed via special address modes and instructions. The chip has a fast nonmultiplexed external bus--16 bits for addresses and 8 bits for data.

WDC's 16-bit extension of the 6502, the W65C816S, has a 6502-emulation mode that lets the W65C816S execute 6502 object code directly. The extended versions have a 16-bit accumulator, an index, and stack pointer registers. The W65C816S also added 78 opcodes, nine addressing modes, and a second 8-bit accumulator. Mitsubishi also extended the architecture to 16 bits with its 37700 family.

The W65C816S addresses up to 16 Mbytes; the 6502 has a 64-kbyte limit. The 16-bit CPU generates a 24-bit address by concatenating the 16-bit program or calculated address with an 8-bit bank register (separate bank registers are reserved for program and data).

Power management: The devices have stop and wait low-power modes.

Special instructions: The 6502 and 37400 support bit-manipulation instructions that include set, clear, test, complement, and branch if bit is 0 or 1. Math functions include add, subtract, increment, decrement, and decimal adjust. STP stops clock; WAI waits for interrupt. The 816S performs block moves.

Motorola 68HC05

To date, there are more than 180 versions of the 68HC05. The accumulator-based 68HC05 is a low-end µC with a few registers and a stripped-down 6800 instruction set. The instruction set features 10 uncomplicated addressing modes, including 8- and 16-bit indexing from the 16-bit program counter. In addition to the accumulator, the CPU's core has an index register, a 5-bit stack pointer, and a 5-bit condition-code register.

Power management: The CPU has wait/stop modes: Wait discontinues CPU processing but leaves the clock, timer, serial-peripheral interface (SPI), and serial-communication-interface (SCI) systems enabled. Stop stops the clock and all internal processing. Both modes maintain RAM and enable an interrupt to wake the CPU. Most special peripherals are programmable and can be turned off selectively.

Special instructions: The 68HC05's bit-manipulation instructions are set, clear, test, jump-on-bit-set, or jump-on-bit-clear. The CPU can test and branch on an interrupt bit, but branches are ±127 bytes relative to the PC. Math functions include add, subtract, increment, decrement, and multiply (no divide).

Special peripherals: The 68HC05's timer/counter is built around a 16-bit free-running counter, which is coupled with a 16-bit capture register and a 16-bit compare register. The capture register captures timer values on some line events; the timer/counter continually compares the compare register with the running timer. When the registers match, an output compare flag is set, and an output pin is driven to a programmed value.

Second sources: Harris Semiconductor (Melbourne, FL), Hitachi (Brisbane, CA), and SGS-Thomson (Phoenix, AZ).

Motorola 68HC08

The accumulator-based 68HC08 provides a code-compatible performance extension to the 68HC05 (along with 78 new instructions). Although the CPU only has an 8-bit accumulator, the index register, stack pointer, and PC are extended to 16 bits (the condition code register is 8 bits).

The 68HC08 has a standard internal bus, named I-Bus, that promotes derivatives by making it easy to add existing peripheral modules. All peripherals are memory-mapped. The HC08 also includes the System Integration Module (SIM), which is analogous to the SIM built into all 683xx chips. The SIM incorporates bus-clock generation for the CPU and modules, a watchdog timer, and interrupt and reset control.

Special instructions: The 68HC08's bit-manipulation instructions are set, clear, test, jump-on-bit-set, or jump-on-bit-clear. The CPU can test and branch on an interrupt bit, but branches are ±127 bytes relative to the PC. Math functions include add, subtract, increment, decrement, multiply, divide, and DAA (decimal adjust accumulator).

Motorola 68HC11

The 68HC11 has two 8-bit accumulators, an 8-bit condition-code register, two 16-bit index registers, a 16-bit stack pointer, and a 16-bit PC. The CPU can address the two accumulators as a single 16-bit accumulator.

Addressing is restricted to a 64-kbyte unified address space. Some versions have a memory-extension unit that expands addressing up to 1 Mbyte using bank-switched paging. Two memory windows in the 64-kbyte address space map into a 1-Mbyte space. The CPU can directly access memory-mapped I/O (on-chip peripherals).

The 68HC11s run in single-chip mode using only on-chip memory resources or expanded mode. In expanded mode, some I/O ports are replaced with an address/data bus to access external memory. Both multiplexed- and nonmultiplexed-external bus versions are available. Some versions have programmable chip selects.

Power management: The CPU has wait/stop modes: Wait discontinues CPU processing but leaves the clock, timer, serial-peripheral interface (SPI), and serial-communications interface (SCI) systems enabled. Stop stops the clock and all internal processing. Both modes maintain RAM and enable interrupt to wake the CPU. Most special peripherals are programmable and can be turned off selectively.

Special instructions: The 68HC11's bit-manipulation instructions are bit set, clear, test, and jump if bit is set or clear. Math functions include add, subtract, increment, decrement, divide, and multiply. Instructions also swap accumulators, exchange accumulator and an index register, transfer SP+1 to an index register, and set the stack pointer from an index register. A wait-for-interrupt instruction increments the PC, puts all registers on the stack, halts, and waits for an interrupt.

Second source: Toshiba (Irvine, CA).

National Semiconductor COP8

The COP8's accumulator-based architecture includes six to eight control and data registers, one of which is an 8-bit program status register. The CPU also includes two 8-bit address registers, a 16-bit stack pointer, and a 15-bit PC, which the CPU can access as upper and lower 8-bit registers.

The COP8 executes an add, shift, or load in one internal clock (1-µsec period). The instruction set is very compact and relatively simple--77% of the operations execute in one clock and take only one byte. One reason for the compact instructions is that the entire architecture (except the accumulator) is memory-mapped--even the peripherals. COP8 chips can run with external memory for debugging and prototyping code. An 8-bit port serially reads from and writes to external memory and provides emulation control.

Power management: The COP8's clocks can be slowed to minimize power dissipation. Two power modes--halt and idle--cut power losses further. Idle restricts peripheral operations; halt stops the clock. Both modes maintain RAM and enable an interrupt to wake the CPU. Most special peripherals are programmable and can be turned off selectively.

Special instructions: The COP8's bit-manipulation instructions include set, clear, various logic instructions, and bit-test-and-skip to next instruction. Math functions include add, subtract, increment, decrement, decimal correct, and complement. Instructions also swap accumulator nibbles and exchange accumulator and memory. Other special COP8 instructions include decrement-register and skip if zero, return-from-subroutine-and-skip, and software-trap interrupt.

Oki nX 65K

Oki's 65K series chips combine an 8-bit core with an 8-bit bus. Although these µCs are not code-compatible with the 8051, a translator package (and some handiwork) can translate code from one to another. Oki also sells an nX 66K series, an extension of the 65K core with a 16-bit core and an 8-bit bus. The nX 65K has four sets of 16 local registers mapped into data memory. One set acts as the current set for processing; switching to a new set makes for a fast context switch because no registers have to be saved. Four of the 8-bit registers in each set can function as two 16-bit registers for addressing. The 65K core also has two accumulators, a stack pointer, a program status word (PSW), and a 16-bit PC.

The 65K series chips have a single 64-kbyte address space for instructions and data. Memory-mapped SFRs control the peripherals. There are no specialized data-memory segments that require special addressing or logically overlap other segments. The 65K blocks local memory into 256-byte pages referenced when enabled by a field in the PSW. Code can address paged memory using 8-bit registers. Main-memory accesses require 16-bit addresses. The 65K makes a distinction between local, 8-bit, addressable paged memory and general, 16-bit, addressable memory.

Power management: Halt mode discontinues the CPU function with peripherals still functioning. Stop mode stops the clock and all functions other than interrupt. New devices have a dual clock.

Special instructions: The nX 65K's bit-manipulation instructions are set, clear, transfer-to-carry, jump-on-bit-set, and jump-on-bit-clear. Math functions include add, subtract, increment, decrement, multiply, divide, and decimal adjust after add or subtract. The CPU also has a parity check instruction.

SGS-Thomson ST6

The accumulator-based ST6 is a low-end µC with a few 8-bit registers (two index, two general-purpose, and an accumulator) and a 12-bit PC. All basic arithmetic operations involve the accumulator as one parameter and end by placing a result into the accumulator. However, the ST6 is not a classic accumulator-based CPU. Loads are a bit more flexible; the accumulator can be either the source or destination. Also, both memory and registers can be incremented or decremented directly without passing through the accumulator.

Registers and peripherals are memory mapped in the chip's address space. To configure a peripheral or send or receive data to or from a peripheral, a program simply writes to or reads from the peripheral's memory registers.

The ST6 has a six-level fixed stack used to hold the PC on subroutine calls or interrupts. The stack is not user accessible, and, therefore, the CPU does not have a stack pointer register. If the stack is full and a call or interrupt occurs, the current PC value gets pushed onto the stack, all stack entries move down one, and the last entry (first in) is lost.

The PC directly addresses up to 4 kbytes of program memory. A banking scheme that uses a dedicated memory-mapped banking register can expand the program memory. The lower 2 kbytes of ROM can be banked, which provides access to higher 2-kbyte pages in program memory (ranging to 20 kbytes). Program memory can also hold constants or tables, which the CPU accesses via a 64-byte memory-mapped window in RAM that maps into ROM.

Power management: The CPU has wait/stop modes: Wait discontinues CPU processing but leaves the peripherals enabled. Stop mode, entered after disabling the watchdog, stops the clock, peripherals, and all internal processing. Both modes maintain RAM and enable interrupt to wake the CPU. Most peripherals are programmable and can be turned off selectively.

Special instructions: The ST6's bit-manipulation instructions are set and clear. Math functions include add, subtract, increment, and decrement. Relative jumps are restrained to -15 to +16 locations.

SGS-Thomson ST9

Because of its three address spaces--program, memory, and register file--the architecture of the register-based ST9 resembles that of the Zilog Z8. The CPU manages the 256-byte register file as 14 sets of 16 8-bit general-purpose registers (the 15th set is the system page, and the 16th set is addressed as peripheral registers). Switching from one set of registers to another makes for fast context switching because no registers must be saved or restored. The CPU also contains an 8-bit program-status register.

The ST9 has two internal buses: an 8-bit register bus and a 16-bit memory bus, which also moves instructions. Opcode+displacement is a 2-byte instruction that usually requires two memory fetches; a 16-bit instruction only takes one fetch.

The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. Many opcodes specify byte or word operations--the hardware automatically handles 16-bit operations and accesses.

For interrupts or subroutine calls, the CPU uses a system stack in conjunction with the stack pointer (SP). A separate user stack has its own SP. The separate stacks, without size limitations, can be in on-chip RAM or off-chip memory.

Special instructions: The ST9's bit-manipulation instructions are set, clear, complement, test and set, load, and various logic instructions (AND, OR, and XOR). Math functions include add, subtract, increment, decrement, decimal adjust, multiply, and divide.

Texas Instruments TMS370

The TMS370's register-based architecture has up to 256 8-bit registers in a RAM register file. The CPU can address these registers as registers or as RAM. The processor stack is in the register RAM and is referenced by an 8-bit stack pointer. The CPU also contains a 16-bit PC and an 8-bit program status register. On-chip peripherals and EEPROM/EPROM programming control are accessed through a set of memory-mapped registers in a peripheral file. Each peripheral is assigned a frame of 16 registers in the 16-frame peripheral file.

Although the TMS370 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, load/stores, and memory/register and memory/memory exchanges.

Power management: The CPU has standby/halt modes: Standby stops the internal clock in every module except the timer 1 module (used to bring the CPU out of standby). Halt stops the internal clock, which can be restarted by a reset or external interrupt. Both modes maintain RAM. Most special peripherals are programmable and can be turned off selectively.

Special instructions: The TMS370's bit-manipulation instructions are set, clear, complement, and jump if bit is 0 or 1. Bit instructions operate on registers in register or peripheral files. Math functions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. The CPU has some 16-bit operations, such as word moves (a register pair) and incrementing a word, and it uses 16-bit offsets for jumps and register pairs as an address for subroutine calls.

Zilog Z8

The Z8's core is a register-file-based architecture with up to 256 8-bit registers in RAM. On-chip peripherals are memory-mapped and accessed through the register file. The RAM also holds the I/O control registers, 16-bit stack pointer (two registers), and register pointer. The CPU contains a 16-bit PC and an 8-bit program status register. In addition to the register file, the Z8 architecture has 64-kbyte-code and 64-kbyte-data address spaces. The Z8 uses external memory for both code and data spaces. References to external memory are only loads or stores; data manipulation is confined to operations between on-chip registers. For interrupt-driven applications, the stack may be located off chip.

Some Z8-based chips have the Z8 core plus a DSP engine with a 24-bit ALU; other chips support IR remote with IR demodulation timers.

Power management: The Z8 has two standby modes: halt and stop. Halt turns off the internal CPU clock while the timers and interrupts remain active. Stop turns off the internal clock and reduces standby current.

Special instructions: The Z8 does not perform bit-manipulation instructions. Math functions include add, subtract, increment, and decrement. Some devices support 16x16 MPY, 32/16 DIV. The versions with integrated DSPs perform MAC operations. Z8 chips have complex instructions that help minimize coding multiple operations, such as fetching and operating on data and incrementing address pointers.

Second sources: SGS-Thomson (Phoenix, AZ) and VLSI Technology (San Jose, CA).

Zilog Z180/380

The Z180 core is a dual-accumulator-based architecture with two flag registers and duplicate sets of six 8-bit general-purpose registers. All 8-bit arithmetic/logical operations use the accumulator as source and destination. Compare operations also are relative to the accumulator. To maintain compatibility with the Z180, the Z380 register set is a superset of the Z180. The most significant extension the Z380 offers is a 16-bit data bus. Registers are 32 bits wide.

Special 16-bit registers make addressing much easier for programmers. These registers include two index registers, a stack pointer, a PC, and an interrupt register. The interrupt register holds the eight upper address bits for interrupt vectors. The chip also has an 8-bit memory-refresh register, which uses the lower address bits for memory refresh.

The Z180 family relies on off-chip memory. In the 8-bit world, the Z180 is ideal for large-scale memory-to-memory operations. To simplify addressing, the CPU does 16-bit accesses (two 8-bit words accessed sequentially). With internal MMUs, the Z180 and Z380 access 20- and 32-bit physical addresses, respectively.

Power management: The Z180 has two standby modes: halt and stop. Halt turns off the internal CPU clock while the timers and interrupts remain active. Stop turns off the internal clock and reduces standby current. Sleep mode, available on the Z180 and Z380, stops the CPU while on-chip peripherals are active.

Special instructions: The Z180's bit-manipulation instructions are set, reset, or test a bit in register or memory location. Math functions include add, subtract, increment, decrement, and decimal adjust. You can perform most math functions as 16-bit operations using register pairs. The Z180's complex instruction set provides many programming options, including block-memory moves up to 256 bytes and character searches within a block. The Z180 includes a multiply, extra-test, and I/O instructions. The Z380 expands on the instruction set of the Z180. Most instructions can be executed with 16-bit-wide operands and results. The Z180 also performs divide instructions. The Z380 employs decoder directives that tell the instruction decoder that the instruction is extended by word or byte.

Second sources: Hitachi (Brisbane, CA), NEC (Mountain View, CA), SGS-Thomson (Phoenix, AZ), Sharp (Mahwah, NJ), Toshiba (Irvine, CA), and VLSI Technology (San Jose, CA).