Troubleshooting interrupts and DMA requests on the ISA bus can be tedious and time-consuming without the appropriate tools. A digital storage oscilloscope or logic analyzer works well, but LEDs are usually fine for monitoring buffered interrupt- and data-request lines. According to the ISA bus specifications, a low-to-high transition on these lines asserts a request. Therefore, the monitor should contain an edge-triggered flip-flop for each line (Fig 1a). This arrangement may suit SSI logic, but it does not suit PLDs with a common clock. To use PLDs, you need a synchronous state machine that detects the low-then-high sequence for each request line. The circuit requirements would be two flip-flops per channel or four channels per GAL20V8.

Asynchronous latches provide a cheaper solution. Unfortunately, the behavior of unused request lines depends on the motherboard. These lines can either have pullups or be floating. Thus, you could obtain false readings when driving latches directly from bus lines. Yet, you need only to trigger a latch at the rising edge and keep the LED on until manual reset. The capacitors come in handy, because a capacitor in series with the GAL's input and pulldown resistor form a simple highpass filter (Fig 1b). Positive edges preset the latch, and the GAL's internal diode clamps any negative overshoots. The result is eight channels per GAL20V8