Design Feature:September 28, 1995

As companies struggle to shrink the time needed to transform products from mere ideas to working units on dealers' shelves, test departments feel unprecedented pressure to speed up pc-board test-process development. Fortunately, today's surface-mount pc boards exhibit a spectrum of faults much different from those that plagued through-hole boards. In response to these new realities of board test, automatic test equipment (ATE) suppliers are offering systems that track down opens and other process-related faults without time-consuming test-vector development.

Picture One

Nevertheless, designers who create densely packed boards that offer limited nodal access are living in a fool's paradise if they think that figuring out how to test the boards is someone else's problem. For the most part, the way to solve test-access problems is in design. Designers must make sure--long before there are any boards to test--that access problems won't exist. Still, you need not lock yourself into a time warp to design testable boards. The through-hole-mounted components of a bygone era and the design rules that went with them don't address the problems of 1995.

Over the last decade, several trends have almost completely transformed pc-board manufacturing and test:

• Surface-mount technology has completely changed the most common types of process faults. On through-hole boards, the most common process faults were solder shorts. Now, opens are the most prevalent faults, followed by misoriented, misaligned, and missing components.
• Dramatic improvements in IC quality make it reasonable for board assemblers to assume--without testing--that the ICs on a board are good.
• The nearly universal use of ASICs often means that the data needed to develop board-test vectors are either unavailable or are not available in a timely manner.
• Shortened product life cycles and outsourcing of assembly and test allow almost no time for board-test process development. In addition, even more than in the past, the people responsible for test processes neither know nor want to know how boards work.

These trends have motivated pc-board ATE suppliers to devise "vectorless" test methods (seebox, "For free information..."). Vectorless techniques do not require developing test vectors to locate open circuits and assembly errors. To understand some of the newer methods, it is helpful to compare them with older vectorless test techniques--manufacturing-defects analysis (MDA) and analog-signature analysis (ASA).

Picture Two

Vectorless techniques (Table 1) rely on measuring a variety of parasitic properties of devices on the board under test. In most of these measurements, the board under test is not powered up. Examples of measured parameters are current through protective diodes and parasitic transistors and capacitance between pc traces and IC lead fames.

All of the techniques require nodal access. Usually, the test system applies signals to device pins and measures the resulting signals on other pins or on sensors pressed against the devices. The actual contact points are almost always pads on traces that connect to the desired circuit points. Unlike test points on through-hole boards, the access points are rarely, if ever, on the device leads themselves and are often many inches away.

Although vectorless testing can find the most prevalent faults on modern surface-mount boards, it is not the panacea some proponents want you to think it is. Mark Yelinek, principal test-process engineer at Digital Equipment Corp, has done extensive evaluations of vectorless-test systems from several ATE vendors. He claims credit for inventing the term "vectorless test." Although Yelinek sees considerable value in vectorless techniques, he thinks that ATE suppliers must do more to make board assemblers feel comfortable with vectorless approaches.

Because vectorless test does not use vectors, test development consists of having the test system "learn" the characteristics of known-good boards. A problem inherent in this approach is that normal process variations can cause wide variations in the measurements on which the systems base their judgments of what is good and what is bad. According to Yelinek, what test supervisors want is the ability to prove that a system is making correct decisions. The ability to purposely introduce faults and have the system locate them would be a great confidence builder. Unfortunately, vectorless-test systems look primarily for open circuits, and introducing open circuits requires damaging boards on purpose.

You can, of course, build in features such as split pads that are normally bridged by solder. These features let test supervisors introduce open circuits to determine whether the test system locates them. As a practical matter though, adding such "test-the-tester" features to boards risks introducing problems just as serious as test escapes--board faults that escape detection by the tester.

Vectorless techniques fall into an area usually called process test (PT). PT aims to isolate faults that relate to the assembly process and to provide early feedback to manufacturing personnel who must correct process problems before many units need rework. PT is just one category of testing performed on pc boards, subassemblies and complete products containing boards and subassemblies. Other types of testing include, but are not limited to, in-circuit, cluster functional, board-level functional, and system-level functional tests.

In theory, PT does not replace the other types of testing. In practice, many companies--particularly ones that emphasize low-cost, high-volume production--simply can't justify the cost of tests that find few defects. Hence, many manufacturers take boards right from PT to system-level functional test. In other words, proven, well-controlled manufacturing processes can reduce, but not eliminate, the need for test. In companies that build mission-critical hardware however, reducing the number of test steps may never gain acceptance.

Interestingly, ATE vendors note definite geographic preferences for certain types of test. Manufacturing-defects analysis is most popular in Asia; vector-based in-circuit and cluster testing are popular in the United States, and board-level functional test dominates in Europe. Vectorless test is relatively new, so it is not yet the dominant technique anywhere. However, vectorless test's popularity is growing everywhere.

Despite its usefulness, vectorless test is no substitute for design for test (DFT). A key reason that vectorless test won't replace DFT is that all of the vectorless techniques for locating open circuits and assembly errors require probe access. Vectorless test is thus merely one item in the arsenal of techniques that enable design and test to cope with ever more dense boards and more complex devices.

Boundary scan

IEEE-1149.1 boundary scan (Ref 1), a technique that uses vectors, allows interconnect testing without probe access. In the world of real devices, however, boundary scan doesn't necessarily do away with all nodal access requirements. Not enough types of scannable ICs exist to allow designing boards exclusively with scannable parts. Even the most ardent boundary-scan advocates envision board designers finding only enough types of scannable devices to fill 80% of their IC needs for the foreseeable future. More realistically, IEEE-1149.1 is likely to appear in only 50 to 60% of devices.

IEEE-1149.1 proponents point out, however, that even if only 50% of the devices on a board conform to IEEE-1149.1, you may be able to use boundary scan to test well over 50% of the board's interconnects. If scannable parts surround each nonscannable IC, you can use the scannable devices' IEEE-1149.1 features to test the connections to the nonscannable parts.

On the other hand, vectorless-test advocates point out that boundary scan is too often less than ideal. Nowadays, suppliers of proprietary ICs such as µCs usually describe their parts in boundary-scan-description-language (BSDL) files. Some electronic-design-automation (EDA) tools used in ASIC design produce BSDL files on request. These files become inputs to automatic-test-pattern-generation (ATPG) software that creates boundary-scan vectors for testing device interconnects.

Picture Three

Although the combination of BSDL and ATPG allows people unfamiliar with a board under test and the devices on it to rapidly generate boundary-scan vector sets, the approach is not without its problems. BSDL errors are still more common than they should be. When the errors occur, they can be disastrous (Ref 2). BSDL errors not only produce inaccurate tests, but they also sometimes cause device damage.

Complementary techniques

In fact, boundary scan and vectorless test complement each other. If boundary scan lets you reduce a board's nodal-access requirements from 2000 to 800, the layout will be much cleaner and the layout job will be easier.

"But, don't produce a layout that simply provides access to the 800 nodes that are easiest to reach," cautions Dr Ken Parker, senior scientist at Hewlett-Packard's Manufacturing Test Division in Loveland, CO. "Start by determining which nodes you can access with boundary scan and provide probe access to the others. Unless you follow this approach, you'll provide direct access to some nodes that don't need it. But other parts of the board will be untestable."

Reducing the need for nodal access offers additional benefits. Boards with simpler layouts usually behave better at high frequencies. Ensuring nodal access by inserting vias and pads in etch runs can degrade high-frequency performance by adding impedance discontinuities. How much trouble such discontinuities cause is a matter of debate, however. Doug Raymond, an engineering manager at Teradyne Inc's Walnut Creek, CA, board-test business unit, believes that detractors of test techniques that require probing exaggerate the deleterious effects of nodal-access features.

"At 100 MHz, one-quarter wavelength is about 2 1/2 feet in free space," Raymond points out. "These discontinuities are no larger than a few millimeters."

Although the techniques used in GenRad, HP, ITA, and Teradyne vectorless testers have been available commercially for only a few years, there is nothing new about the idea of testing boards without developing vectors. Manufacturing-defects analyzers, vectorless in-circuit testers, and analog signature analyzers have been around for a generation. Like the newer systems, the older vectorless testers start by making measurements on one or more known-good boards. The systems store the results of these measurements and compare them with the corresponding measurements on the board under test.

Picture Four

Manufacturing-defects analysis

The simplest type of system, the MDA, was originally developed to test discrete-component analog and mixed-signal boards. MDAs are now widely used on digital boards, however. Checksum is a leading MDA supplier. Most MDAs measure the impedance between pairs of circuit nodes on unpowered pc boards. The systems apply a small audio-frequency voltage to one node and measure the current exiting from a second node that you hope is connected to the first by a component. Usually, an op-amp current-to-voltage converter circuit (I/V) forms the heart of the tester's measurement system. The I/V's op-amp summing junction creates a virtual ground at the node from which current exits.

This technique allows the use of guarding for measuring individual component values. By grounding nodes surrounding the circuit element under test (in other words, by guarding the summing junction), the system can eliminate unwanted components from its measurements.

For example, guarding enables individual measurements of each of three two-terminal components in a triangular configuration. To measure one component, the tester drives one node, connects a second node to the I/V summing junction, and grounds the third node. Although this approach does not allow separate measurements of components connected in parallel, further refinements, such as the use of phase-sensitive detectors, sometimes make it possible to determine the value of a capacitor connected in parallel with a resistor.

The ASA is a refinement of the MDA. ASAs are based on the idea that semiconductor devices' nonlinearities contain useful information. Like MDAs, ASAs apply ac signals to board-under-test nodes. Instead of assuming that the impedance between a pair of nodes is linear, however, an ASA determines the shape of the I-vs-V curve, that is, the Lissajous figure that represents the nonlinear impedance between the nodes. Two suppliers of ASAs are Huntron and Polar Instruments.

Modern ASAs used in production test usually digitize and store the I-vs-V curves measured between each node of the known-good board and ground or V_CC. The systems establish guard bands around these curves and base their good-vs-bad judgments on whether the curves acquired from the board under test fall within the guard bands.

Whereas MDAs have historically used bed-of-nails fixtures, the original ASAs did not. The first applications of ASAs were in board repair, where technicians would manually probe each defective board. Such early ASAs and some low-cost units that are still being sold do not store curves acquired from known-good boards; instead, technicians compare acquired waveforms with scope photos of known-good-board waveforms.

As suppliers of ASAs moved their products out of board repair and into production test, they added features. Besides the ability to store and make comparisons with known-good-board waveforms, the systems added bed-of-nails fixturing and switching matrices to connect the test points to the measurement system.

Some systems offer additional probing options. Instead of using bed-of-nails fixtures dedicated to specific boards, systems intended for testing many board types (each in small quantities) sometimes use servo systems to position the probes on the test points. The servo-positioning technique also appears in ITA's Flying Scorpion system, a vectorless tester based on semiconductor-junction (P-N junction) measurement technology.

At least in theory, both MDAs and ASAs can pinpoint the exact locations of open circuits on boards under tests. However, the ATE vendors who supply vectorless-test systems maintain that the capacitive, inductive, and P-N junction measurements that their systems make do a better job of locating defects.

But in the case of the capacitive and inductive techniques, there is a price. Unlike MDAs, ASAs, and testers based on junction measurements, testers that use capacitive and inductive techniques require overclamp fixtures. The tester doesn't merely press, or suck, the board under test down onto a bed of nails, it sandwiches the board under test between the bed of nails and the overclamp apparatus.

In the view of many users, the ability to work without overclamp fixtures makes junction-based techniques the most desirable of the vectorless techniques offered by ATE suppliers. A controversy rages among several of the vendors on just what fraction of process faults junction-based vectorless testing can detect, however. For certain, no junction-based technique can find interconnect problems in components that don't have junctions--connectors and IC sockets, for example. All vectorless techniques for finding interconnect problems with such devices use overclamp fixtures.

Teradyne aggressively promotes three types of vectorless test: junction-based, capacitive, and RF-inductive. The company provides tools for evaluating which type of testing is likely to do the best job on particular boards. Teradyne also offers a system called Safecracker. By making measurements on ICs for which design information is unavailable, Safecracker automatically generates vectors for testing the devices' interconnects.

Picture Five

GenRad's position on vectorless test is now similar to Teradyne's. GenRad recently began offering a junction-based capability in addition to the capacitive testing it has provided for several years. Like several of its competitors, GenRad also offers tools for locating misoriented components and polarized capacitors that have been inserted backwards. HP's vectorless opens-test offerings use capacitive technology. HP has worked on and patented junction-based testing but does not use the technology in products.

ITA's vectorless testing uses P-N junction technology. According to Jack Ferguson, ITA's general manager, the company's technique measures currents in parasitic transistors and differs from other suppliers' diode-based approaches. Ferguson says the technique isolates the IC under test from other ICs on a bus, allowing ITA systems to test bused connections. Although ITA maintains that its customers have no need for capacitive or inductive techniques, the company offers vector-based testing.

Capacitive opens testing

The easiest to understand of the vectorless technologies is the capacitive type. The tester applies a small high-frequency ac signal to each circuit node in turn. A transducer pressed against the top of the IC package senses the signal. The lead frame within the IC package becomes one plate of a capacitor; the sensor is the other plate. What actually forms the first plate is not the lead frame but what remains of it--the portion that connects the exposed leads to the die. The IC manufacturer removes most of the frame after encapsulating the die.

If the connection between the probe point on the pc board and the lead frame is intact, the current that flows in the sensor is large compared with the current that flows if the connection is open. An open connection places a small capacitance in series with the relatively large capacitance between the lead frame and the sensor. The small capacitance limits the sensor current. This technique works well only with packages whose capacitance to the sensor is fairly large. Many ball-grid-array packages don't use lead frames and hence exhibit small capacitance to the sensor.

The RF-inductive technique replaces the capacitive sensors atop each IC package with magnetic inducers, or coils. The system sends an RF current, a few hundred kilohertz, through the inducers one at a time. Instead of applying an ac voltage to the circuit nodes, the system grounds each node in turn and measures the current flowing in the grounded node at the inducer-signal frequency.

Junction-based testing

Teradyne's junction-based technique uses the normally back-biased protection diodes between the input and ground pins of CMOS and bipolar digital ICs. Most mixed-signal ICs also contain such diodes. The ICs are unpowered during test. The tester makes groups of measurements on pairs of pins. It does so by performing the following steps: (In all steps, the IC's normal ground pins are connected to ground.)

In the first step, the tester applies a negative dc voltage (with respect to ground) to the first pin of a pair and measures the current through the pin. The applied voltage forward biases one of the protective diodes. While maintaining the voltage on the first pin, the system applies a slightly more negative voltage to a second pin to forward bias a second diode. Next, the system measures the change in current through the first pin. A connection problem exists if there is no change. The system makes six measurements on pin pairs to localize connection problems to individual pins.

ITA's version of junction-based test uses parasitic transistors that exist in ICs whose internal transistors and FETs are junction-isolated from the substrate. Nearly all ICs use junction isolation. The parasitic transistors in almost all modern ICs are NPN, and the polarities in the following discussion apply to such devices. Although the parasitic transistors have h_FEs much lower than 1, you can bias the transistors into a linear conduction mode by

• grounding the IC substrate, normally, the IC's ground pin
• applying an appropriate negative voltage to a device pin connected to an N-doped region
• applying a positive voltage to a pin connected to a different N-doped region.

The IC's ground pin acts as the transistor's base; the negatively biased pin is the emitter, and the positively biased pin is the collector. Varying the base-emitter voltage varies the collector current. According to ITA, the three-pin transistor test inherently isolates the pin under test from other connections to the net on the circuit board. Moreover, ITA asserts that the three-pin test detects incorrect device orientation, incorrect devices, cold-solder joints, and static-discharge damage.

Picture Six

Quick and economical

Prices for vectorless test systems, most of which also include a vector-based, in-circuit test capability, begin at under $50,000. The price points vary among the vendors, however. Entry-level prices for MDAs and ASAs are even lower. Testers that combine vectorless and vector-based testing are well suited to testing with a combination of IEEE-1149.1 and vectorless techniques.

Vectorless opens testers, MDAs, and ASAs all offer fast testing and extremely low test-development time and cost. Except possibly for amortization of the tester's purchase price, the largest cost element is the cost of the fixture, or, in the case of techniques that require an overclamp, the fixtures. Fixture costs, of course, depend on the board size, the number of probes, and, for overclamp fixtures, the number of capacitive sensors or magnetic inducers. You'll find one fixture vendor listed in the box, "For free information...".

Aside from specifying the fixture and waiting typically from one to three weeks for the fixture vendor to deliver it, the time required for test development is minimal--often under an hour. Updating the tests to reflect design changes also takes only minutes, except when a layout change necessitates a fixture change. Test time is also quite fast; one user reports that tests to a board with over 1000 nodes take only two minutes.

You can reach Senior Technical Editor Dan Strassberg at (617) 558-4205, fax (617) 928-4205. e-mail:ednstrassberg@cahners.com

References

1. Strassberg, Dan, "Boundary-scan testing," EDN, Oct 14, 1993, pg 78.
2. Sherman, Jeff, "To use BSDL successfully, validate device descriptions carefully," EDN, June 8, 1995, pg 127.
3. Scheiber, Stephen, Building a successful board-test strategy, Butterworth-Heinemann, Newton, MA, 1995. ISBN 0-7506-9432-7.
4. Twenty-fifth anniversary compendium of papers from the International Test Conference, IEEE Computer Society Press, Los Alimitos, CA, 1994. ISBN 0-8186-6617-X.