Design Feature: September 28, 1995

Design innovations provide for voltage-tunable, state-variable active filters for megahertz ranges

Chris Siu,
Elantec Corp

A new generation of wideband amplifiers and multipliers allows you to build state-variable active filters that operate beyond the kilohertz region into the megahertz region. Using these devices and appropriate design techniques provides a very linear tuning characteristic.

Two important characteristics in filter design are the cutoff frequency and selectivity (Q). With passive RC networks, the Q is limited because the poles must lie on the negative real axis in the s plane. Although passive RLC networks can have greater Q through complex conjugate poles, their use of large, nonideal inductors often prohibits the use of these networks. By using active elements within RC networks, however, you can shift the poles off the real axis and provide good selectivity without resorting to inductors. In addition, these active filters can provide passband gain, which is not possible with passive circuits.

Reviewing some basic state-variable filter-transfer functions provides you with a strong base from which to begin. The biquadratic function is:

where [smlomega]0 is the resonant frequency, and Q is the quality factor. H(s) is lowpass if K₁ and K₂=0. Similarly, H(s) is highpass if K₁ and K₀=0 and bandpass if K₂ and K₀=0.

One possible active filter is the state-variable configuration of Fig 1a. You can obtain lowpass, highpass, and bandpass functions by tapping different points in the diagram. Fig 1b shows an implementation using three op amps. The design equations for this circuit can be confusing because of the many independent variables. However, adding some constraints can simplify these equations considerably.

Note that integrator-time constants R₁C₁ and R₂C₂ control cutoff frequency. To make this filter tunable, you can modify these time constants by changing the resistance values, using the current-mode multipliers (Fig 2). The multiplier takes the current through the integrator resistor, scales it by a factor determined by tuning voltage V_G, and outputs this current into the integrator. By controlling both multipliers with the same V_G, you have a linear relation between cutoff frequency and V_G:

(Note: 95 Ohms is the input resistance of the EL2082 current-mode multiplier)

For example, if you are designing a tunable second-order Butterworth (maximally flat) filter, your design requires Q=0.707. Suppose you want a passband gain of 0 dB. Referring back to the design equations, you can meet this requirement by constraining R₃=R₄ and R₅=R₆. Thus, the design equations for ê0 and Q simplify to:

To set Q=0.707, make the second integrator time constant twice as large as the first one. Fig 2 shows a design with Q=0.707 and f₀=750 kHz (at V_G=1V). Figs 3a and 3b show the response of this filter, measured at the lowpass and bandpass outputs. The response is quite close to the theoretical values. Fig 4 shows a voltage-vs-frequency plot for this filter, where we see that the filter is tunable from about 150 kHz to 1.5 MHz, with a linearity error of less than 1%.

Problems at higher frequencies

Generally, the active filter shown works well below 1 MHz, where many op amps have ample open-loop gain and parasitics are negligible. As you increase the frequency of operation, however, both limitations of the op amps as well as parasitics become dominant, in some cases making the filter oscillate (see box, "Op amp limitations play a role").

Op-amp limitations play a role.
One source of limitation in this circuit comes from the integrator op amps. Because these integrators are inside feedback loops, they should have close to 90° of phase shift. If the integrators deviate substantially from 90°, the output of the summing amplifier will grow, just as if Q has been increased from its nominal value. PSpice (from Microsim Corp, Irvine, CA) simulations of the state-variable filter illustrate the problem. In the output of the summing amplifier with ideal op-amps and Q=0.707, no peaking occurs. Retaining an ideal op-amp for the summer but using 60-MHz op-amps for the integrators (only 82° of phase shift at 10 MHz) results in 1.5 dB of peaking. Another source of problem comes from the current-mode multipliers, which each have approximately 3 nsec of delay. These delays introduce additional phase shifts inside the feedback loop. To see the severity of this problem at higher frequencies, you can modify the circuit in Fig 2 by changing C₁ to 15 pF and C₂ to 30 pF. This change increases the cutoff frequency to 7.5 MHz (V_G=1V). However, the lowpass response exhibits close to 1dB of peaking, moving the 3-dB bandwidth to 10 MHz. The peaking gets more severe as V_G is increased to raise the cutoff frequency. Fig A shows how peaking and 3-dB bandwidth vary with V_G in this circuit, as the circuit strays far from its intended behavior at V_G=2V, with a tendency toward oscillation. In general, op amps in the integrator section should have at least 20 dB of open-loop gain at the filter cutoff frequency. For example, a 10-MHz filter requires op amps with at least 100 MHz of unity-gain bandwidth. Because the current-mode multipliers also introduce delay, this 20-dB margin would not be sufficient without using a higher speed op amp or the compensation described in this article.

Op-amp limitations play a role.

One source of limitation in this circuit comes from the integrator op amps. Because these integrators are inside feedback loops, they should have close to 90° of phase shift. If the integrators deviate substantially from 90°, the output of the summing amplifier will grow, just as if Q has been increased from its nominal value.

PSpice (from Microsim Corp, Irvine, CA) simulations of the state-variable filter illustrate the problem. In the output of the summing amplifier with ideal op-amps and Q=0.707, no peaking occurs. Retaining an ideal op-amp for the summer but using 60-MHz op-amps for the integrators (only 82° of phase shift at 10 MHz) results in 1.5 dB of peaking.

Another source of problem comes from the current-mode multipliers, which each have approximately 3 nsec of delay. These delays introduce additional phase shifts inside the feedback loop. To see the severity of this problem at higher frequencies, you can modify the circuit in Fig 2 by changing C₁ to 15 pF and C₂ to 30 pF. This change increases the cutoff frequency to 7.5 MHz (V_G=1V). However, the lowpass response exhibits close to 1dB of peaking, moving the 3-dB bandwidth to 10 MHz. The peaking gets more severe as V_G is increased to raise the cutoff frequency. Fig A shows how peaking and 3-dB bandwidth vary with V_G in this circuit, as the circuit strays far from its intended behavior at V_G=2V, with a tendency toward oscillation.

In general, op amps in the integrator section should have at least 20 dB of open-loop gain at the filter cutoff frequency. For example, a 10-MHz filter requires op amps with at least 100 MHz of unity-gain bandwidth. Because the current-mode multipliers also introduce delay, this 20-dB margin would not be sufficient without using a higher speed op amp or the compensation described in this article.

Although an integrator is fairly tolerant of stray capacitance at its output, you should ensure that the capacitor leads around the feedback path are as short as possible. Compare the difference between soldering the capacitor directly across the input and output vs having 2 in. of wire on each side. In actual measurements, this results in a 750-kHz decrease in unity-gain frequency (from 7.6 MHz to 6.85 MHz) and a 4° loss in phase (89 to 85°). Because the state-variable filter uses multiple feedback and both integrators are inside the overall feedback paths, your design should maintain as close to a 90° phase through each integrator as possible.

You should try to minimize stray capacitance, and you should also give particular care to the inverting input of the summing amplifier. Any stray capacitance here would cause unwanted phase shifts due to R₅ and R₆. These phase shifts would alter the filter's response. You should practice soldering R₅ and R₆ onto the inverting input and remove the ground plane surrounding this node.

Each current-mode multiplier introduces 3 nsec of delay in the feedback path. Although this delay introduces negligible phase delays at low frequencies, the resultant delay is a problem at higher frequencies. At 10 MHz, 3 nsec is equivalent to a 10.8° phase delay, and, at 20 MHz, this phase delay increases by 21.6°. This increase is one reason why the peaking became so severe in the circuit when you tuned V_G from 1 to 2V.

To compensate for this delay, you can add a capacitor across R₁ and R₂ (in this case, 3 pF). This parallel RC combination introduces a zero in the feedback path and adds some positive phase that was lost because of the multiplier delays. With this compensation, peaking is kept below 1 dB throughout the entire tuning range, compared with over 5 dB of peaking in the uncompensated case.

This compensation technique does have its limitation, however. The parallel RC circuit increases feedthrough at higher frequencies and can disrupt the stopband response. Fig 5 shows some actual measurements for both the uncompensated and compensated cases. Although the uncompensated response shows peaking, its stopband rolls off monotonically at 40 dB/ decade. In contrast, the compensated response has minimal peaking, but its stopband has aberrations that disrupt the roll-off.

Reference

Chen, Carson, Active Filter Design, Hayden Books, Indianapolis, IN, 1982.

Author's biography

Chris Siu designs high-speed bipolar ICs at Elantec Corp, Milpitas, CA. His designs include current-feedback amplifiers and sample/hold circuits. Siu holds an MS from Stanford University, Stanford, CA.