Design Ideas September 28, 1995

The validation circuit in Fig 1 allows you to check the consistency of successively recurring 3-bit address codes. The circuit simultaneously applies the address code to the A port of IC₂, a 7485 magnitude comparator, and to IC₃, a 1-of-8 decoder. When IC₂'s B port reads the same address latched on the output of D flip-flop, IC₁, O_A=B goes high, thus enabling IC₃. IC₄'s 4-bit counter counts the number of successive enables sent by IC₂. Once the counter reaches the required number of validations, IC₄ generates its own enable for IC₃.

At start-up, O_A=B is low, which disables E₂, and IC₄ is preset to zero. At the onset of the first address code, IC₂ compares this code with the contents of IC₁. Because the contents will be different, O_A=B remains low, enabling PE. At the arrival of the clock pulse, IC₄ is again preset to zero, and IC₁ loads the first address code.

The circuit again compares the next address code with the contents of IC₁. If they are identical, O_A=B goes high, enabling E₂ and disabling PE. Consequently, the following clock pulse increments the count of IC₄. When the circuit attains the required number of validations, the Q₂ output of IC₄ goes high and completely enables IC₃. If you need more validations, you can cascade additional 74161 counters.