Design Feature: October 12, 1995

One of the first digital-cordless-telephone standards to be implemented is the Digital European Cordless Telecommunications (DECT) standard. The Pan-European standard employs the time-division-duplex/ time-division-multiple-access (TDD/TDMA) technique, which uses separate time slots on a carrier for transmitting and receiving signals. DECT accommodates multiple users by assigning different time slots to different users. This method requires the transmitter to be turned off while receiving and the receiver to be turned off while transmitting.

The DECT standard is a challenge to implement at the system level simply because you must address the effects that require simulation simultaneously to observe and improve the performance of the system. The frequency allocation for DECT comprises 10 channels numbered 0 through 9. The data rate is 1.152 Mbps, and the bandwidth/bit time product is 0.5. DECT uses the Gaussian frequency-shift-keying modulation technique.

Table 1 lists the frequency allocations in a low sideband-injected configuration. Fig 1 shows the structure of the TDD/TDMA frame. A complete frame is 10 msec long and subdivides into two subframes: 5 msec for the transmission of the fixed point (FP) and 5 msec for the transmission of the portable point (PP). Each subframe further divides into 12 480-bit-long time slots. When the communications link occurs, DECT assigns time slots to the users. Normally, DECT assigns the same time slot number for both receiving and transmitting. Therefore, by using TDD, the receive and transmit functions cannot operate simultaneously. Fig 2 shows a bit-level view of the time-slot structure. The guard space (GS) allows a sufficient interval for the transmitter output power to subside, preventing leakage into the next slot.

The PLL is a central component in the design of the telephone, because the synthesizer that generates the signals for the telephone's receive and transmit functions depend on the PLL. The PLL controls the carrier frequency of the transmitter and the local-oscillator frequency of the receiver. The PLL also maintains a fast switching time and a small lock time and minimizes spurious-noise effects.

Lock time is the time the PLL takes to switch from one frequency to another within a given tolerance. Spurious noise, or reference feed-through spurs, is the level of the reference side tones relative to the desired tone. This relationship creates a trade-off between faster switching performance of the PLL and the degradation due to spurious noise. Faster switching times mean higher spurs. The architecture for the design of the PLL includes a variable modulus divider to convert the oscillator frequency down to the reference frequency. In this case, a reference frequency of 1.728 MHz is compatible with the DECT standard and is equal to the channel spacing. The synthesizer must span the DECT frequency band for both transmitting and receiving functions. The PLL requires a VCO tuning range with a maximum frequency deviation of 130 MHz and a switching speed of 35 to 400 µsec.

The design of the PLL begins with the calculation of the loop-filter parameters. The loop filter's performance is largely a function of the loop natural frequency or the settling time of the PLL.

In the above equation, (omega)_n is the loop natural frequency, and t_s is the settling time. The settling time in this example is 40 µsec. This time allows the PLL to settle fast enough between receiving and transmitting frames. Choose an oscillator with a tuning range of 130 MHz and a tuning sensitivity (K_v) of 65 MHz/V to meet the frequency variation to generate the receiver LO and the transmitter carrier frequencies. We can assume a damping factor (rho) of 0.9 and a gain of the charge pump K_pof 0.001. A calculation of the third-order loop parameters given the values for (omega)_n, K_v, and K_p yields c₁, c₂, and r₂, as the following equation shows:

The lock times for the calculated parameters are approximately 40 µsec (Fig 3). Fig 4 shows the block diagram of the PLL. You can model prescaler functions, which are typically used in both static and variable-modulus PLLs, with a MULTX function. A phase-frequency comparator and an integrator model the comparator and charge-pump functions. You can modulate the VCO directly by injecting the data onto the control signal of the VCO. A Gaussian filter shapes the binary transmitted data to limit the spectral energy in the adjacent channels.

TDD/TDMA-system designs offer many simplifications. For example, the transmitter transmits short bursts of 420 bits or 365 µsec. Fig 5 shows the transceiver block diagram. You can allow the synthesizer to have a small amount (50 kHz) of open-loop drift, which lets you use a single VCO for the modulator during the transmit cycle and the LO source during the receive cycle. The receiver is on for only a short time, because the allowable frequency drift is less than 10% of the discriminator bandwidth. The small frequency drift allows the use of a simple discriminator design instead of complex data-recovery circuitry. The transceiver design uses a low-loss bandpass filter at the receiver input from the antenna to reduce out-of-band interfering signals and to limit excessive wideband transmitter noise and spurious harmonics. A duplexing switch (Fig 6) has less than 1-dB loss and isolates the receiver and transmitter functions.

The receiver in Fig 7c contains a low-noise amplifier (LNA), an image filter, and a mixer. The LNA is a discrete design to improve the noise performance and sensitivity of the receiver. Typically, designers use bipolar transistors to minimize costs. You can place a ceramic filter with three to five poles as an image filter between the discrete LNA and the mixer. The image filter rejects any additional noise from the adjacent sideband. A standard intermediate frequency of 110.6 MHz via an SAW filter is the input to the demodulator. A SAW filter provides low insertion loss and reasonable group-delay characteristics.

The FM demodulator uses a limiter demodulator structure (Fig 7c). A high-gain amplifier limits the signal. The signal mixes with a 90° replica of itself to achieve instantaneous deviation of the input signal. A quadrature tank circuit provides the 90° phase shift to the signal. An important parameter for the tank circuit is the Q of the circuit, which controls the phase-frequency dependency. Ideally, the Q must be high, so that the phase shift vs frequency will be steep and linear. Normally, you can use this type of discriminator circuit only for narrowband signals due to its dependency on the Q of the phase shifter. An IF filter reduces the unwanted IF components and improves the S/N ratio before entering the data comparator. The comparator re-establishes the clock and recovers the data. To derive the timing information, a symbol timing-recovery circuit processes the signal. A PLL achieves the symbol timing by locking onto the rising edge of the discriminated signal. Fig 8 shows a waveform from the output of the discriminator.

The baseband portion of the receiver is responsible for recovering the data and clock, compensating for carrier-frequency drift and baseband filtering of the signal during the transmit cycle. A PLL accomplishes the data and clock recovery. A threshold comparator recovers the clock by detecting the rising or falling edge of the signal. The symbol clock locks onto the incoming data stream by adjusting the clock phase. Fig 9 shows the baseband data and clock-recovery system.

The transmitter contains a Gaussian filter that pulse-shapes the baseband data. The filter shapes the spectral energy, minimizing adjacent-channel interference. The output from the filter connects to the synthesizer VCO-control line through a switch (Fig 4). Opening the feedback loop lets you directly modulate the VCO. You can achieve the same effect without physically opening the loop by using a complex integrator and switch in the PLL system diagram. The synthesizer needs to span the DECT frequency bands for both receiving and transmitting functions. The synthesizer's VCO achieves a fast switching speed of 40 µsec and a frequency jump of 130 MHz. The receiver contains an LNA, an image filter, and a mixer. The output of the VCO connects directly to the power amplifier, which delivers 250 mW of power to the antenna (Fig 5).

Fig 10 shows a prototype DECT telephone. Analog-receiver sensitivity is the signal level needed to produce a required S/N ratio. For digital systems, the sensitivity is the S/N ratio needed to generate the required bit error rate (BER). The DECT standard requires a BER of 10^-3 at nominal temperature using the frequency offsets of +50, 0, and -50 kHz from the received signal. The required sensitivity for the DECT system is 83 dBm. Two figures of merit determine the receiver sensitivity—the receiver noise figure and the demodulator E_b/N_o performance. Fig 11 shows the BER performance, and Fig 12 shows a plot of the BER performance as a function of frequency offset from the received frequency. The figures indicate that an E_b/N_o of 13.6 dB meets the 10^-3 BER requirement and requires an additional 1 dB to compensate for the 50-kHz offset. You can derive the required noise figure for the receiver by knowing the demodulator's E_b/N_o performance. The E_b/N_o ratio equals the S/N ratio of the demodulator at the output of a filter with a noise bandwidth equal to the bit rate r_b.

where Boltzman's constant is k=1.38054x10^-23K/J, the standard temperature is given by T_o=290K, and F_n is the noise factor. Converting the above relationship to decibels yields

Setting E_b/N_o=13.6 dB and the signal level to S_dBm=-83 dBm, which represents the required DECT-signal sensitivity in decibels referred to 1 mW, yields

The front end of the receiver requires an F_dB of 16.8 dB to meet the DECT 10^-3 BER specification.

You can express the receiver's linearity by its third-order intercept point, which is a measure of the signal distortion through the system. Nonlinearity, such as gain compression, in a receiver can cause signals from several transmitters to mix in the receiver. The result is intermodulation products, some of which can have the same frequency as the desired signal. You can measure a receiver's intermodulation performance by using three signals: a desired DECT signal, a modulated interfering signal, and an undesired tone. Set the undesired signals to two adjacent DECT channels and adjust the signal levels of the undesired signals so that their third-order products are of the same frequency as the desired DECT signal. Set the level of the desired signal to its 73-dBm specified value. Set the levels of the two undesired signals to 46 dBm. The third-order intercept point is the point at which the third-order intermodulation product equals the ideal uncompressed output. You can obtain the intercept point by using the expression:

P_IIP3 is the third-order input-intercept point in decibels referred to 1 mW. P_IM3 is the intermodulation product for the two unwanted signals in dBm. P_UW is the power of each of the unwanted signals. P_UW is -46 dBm.

The definition of co-channel interference rejection is the receiver's ability to reject undesired signals appearing at the same frequency as the desired DECT signal. The co-channel rejection ratio is the ratio of the desired signal to the undesired signal that produces the required BER. The rejection ratio for DECT is 10 dB with an input signal level of -73 dBm. A calculation of the P_IIP3 yields 27.5 dBm for a signal level of P_IM3=-83 dBm and an undesired signal level of P_UW=-46 dBm. Table 2 shows the system-receiver budget for the example. The design issues for the receiver are low noise figure, high intercept point, and high gain. The components that control the noise figure and intercept point are the LNA, image filter, and mixer.

1. Philips Semiconductors RF Application Note, JCS/ML 92150, pg 790 to 791.
2. Madsen, B, and DF Fague, "Radios for the Future: Designing for DECT," RF Design, April 1993.
3. Franceschino, A, "Phase-Locked-Loop Primer and Application to Digital European Cordless Phone," Applied Microwave Wireless, Fall 1994.