Design Feature: October 26, 1995

It's a recurring theme: Give careful consideration to "X" early on in your system-design process, rather than as an afterthought. Given the complexity and speed of modern systems, "X" can be just about any part of the system: power sources, pc boards, or connector systems, the subject of this report. As clock speeds continue to increase, connections steadily become more difficult to implement. An unwise choice or the improper application of a connector system can seriously compromise signal integrity and lead to EMI problems.

Because of the diversity of system interfaces, buses, and bus types (mezzanine, Rambus, PCI, et al), this article focuses on the technical considerations involved in designing in a connector system rather than on the details of the myriad available connector types. And "system" is the key word here, as interconnections in high-speed systems pose design issues just as complex as those of the fastest ICs.

As Russ Moser, Amp's internal-support manager, explains, you must use a systems approach when designing in a connector system. Considering a connector "just another component" simply won't work, given the subnanosecond signal edges in many systems. The interaction of a connector with its host system is exceedingly complex—and difficult to specify. For extremely high-speed and complex systems, in fact, your best policy is to work closely with your connector manufacturer from the onset of the design effort. The alternative—afterthought engineering—can lead to costly redesigns.

To borrow from John Donne's famous poem, no part of a system is an island. "Compartmentalized engineering," in which, for example, you design a pc board without regard to the yet-to-be-selected interconnection system, can lead to major problems. The same holds true for the reverse scenario, in which you select a connector system without regard to the characteristics of your pc-board trace geometries. What's needed is a trinity, in which the system designer (you) works closely with both the board fabricator and the connection-system maker from the inception of the design effort.

To assist you in this important trinity, many manufacturers of high-speed connectors maintain substantial staffs of applications engineers. These highly specialized engineers help coordinate your design effort—in both pc-board layout and selection of the appropriate connector system. They also generate connector-system simulation models. Amp, for example, provides single-line electrical-performance models for its catalog parts for simulation under Berkeley 2G6 Spice, PSpice, and ISpice. In addition to connector manufacturers, independent consultants such as North East Systems Associates (NESA) are available to collaborate with systems designers and connector manufacturers.

Organizations such as NESA work closely with both connector manufacturers and connector users to combat thorny problems that arise in the subnanosecond world. NESA President Ed Sayre explains, for example, that unwary designers can fall into the trap of considering a connector interface as part of a well-behaved transmission line. At subnanosecond speeds, however, nonlinearities in material dielectric constants destroy the expected good behavior.

Connector manufacturers often use private testing companies to characterize their products. Samtec, for example, contracted Contech Re-search Inc to perform RF tests on its MOLC and FOLC Series connectors. Contech used time-domain reflectometry (TDR) and other sophisticated techniques to measure the connectors' capacitance, inductance, characteristic impedance, propagation delay, and crosstalk. Such parameters help connector manufacturers develop models for their products.

A "single-line" model, such as those available from Amp, yields the lumped parameters of a given pin with respect to an adjacent pin. Multiple-line models, which define the interactions of a whole array of pins in a connector, are considerably more complex. Amp and other manufacturers develop these multiple-line models in contractual licensing agreements with customers.

In some instances, attempting to "roll your own" interconnection-system design is tantamount to trying to design your own microprocessor. The needed expertise is very specialized, and the necessary testing and system characterization entails some exotic techniques and equipment—for example, EMI-testing equipment and TDR. So, for very high-speed systems, you'll often do well to leave it to the experts. Initially, NRE or consultant fees will cost you, but the alternative could cost a lot more if you have to redesign a system as a result of connector-related gremlins.

When you design a system with subnanosecond edge rates, you enter the world of microwave engineering. Here, nothing is as it seems; lumped parameters become distributed, pc-board traces form transmission lines, and every parameter is a nonlinear function of the edge rate. Impedance discontinuities provoke reflections. In a PCI system, for example, which relies on reflected rather than incident wave fronts, unwanted reflections can be disastrous.

Fig 1 from the Rambus Channel Design Guide (Ref 1) shows the result of inserting a discontinuity in a trace whose characteristic impedance is 50 Ohms. In this case, the discontinuity is a 2.3-pF capacitor; however, it could just as well be the pin-to-ground capacitance of a connector. Fig 1b shows the impedance profile of the trace. You can see that the impedance drops to zero at the point of the discontinuity. In the case of a trace, you can compensate for the discontinuity by narrowing the trace for a certain length (see Fig 1a). In the case of a connector, you'd need to perform other impedance-matching tricks.

Rambus, a de- sign organization that works with partners to provide 500-Mbyte/ sec memory-in-terface systems, imposes rigid re- quirements on pc-board layout, termination rules, and connector pinout. Connectors for Rambus systems, called RSockets, come from Augat and Molex. Odd- and even-numbered maximum pin inductances are specified at 4 and 5 nH, respectively. The maximum allowed pin capacitance for both odd- and even-numbered pins is 3 pF. Fig 2 shows RSockets for vertically mounted (a) and horizontally mounted (b) Rambus modules.

In addition to the specs for particular systems, such as Rambus, international standards exist for the mechanical and electrical characteristics of interconnection systems. DIN 41642/ IEC 1076-4-100, for example, dictates the mating conditions for Harting Electronik's Har-pak system, a 2.5-mm connector family. Harting's literature gives performance curves for both sinusoidal (to 2 GHz) and pulse (0.5- to 2-nsec risetime) pulse inputs. Harting, too, works with customers to develop both single- and multiple-line Spice models for the Har-pak family.

Do some modeling

For relatively simple applications, you can use a connector manufacturer's Spice models to simulate a connector with reasonable accuracy. Fig 3 shows a performance model for the Amp Mictor connector system, a family of 25- or 50-mil-spacing connectors and sockets. The 50-mil model in Fig 3 is a single-line model that simulates the parameters of a given pin relative to an adjacent pin.

This Berkeley 2G6 Spice model gives the lumped-element model with the high-frequency values for resistance, capacitance, and inductance, taking into account mutual inductance and skin effect. It also gives the equivalent, distributed-element transmission-line model of the connector, in which Z₀ is the characteristic impedance and T_D is the propagation time through the connector. Note that the effects of plated through-holes are significant, and you must add them to the models. You can represent a plated through-hole with a 0.5- to 1-pF shunt capacitor.

Note the stipulation in Fig 3: The RLC models are appropriate for edge speeds of 250 psec or slower. As stated earlier, in the microwave domain of subnanosecond edge speeds, the parameters of a connector are nonlinear functions of speed—above a certain speed limit. Amp's Moser states that the most common problem model users have is misusing the models, that is, trying to use a model when the edge speed exceeds the specified value. If you use the model properly, maintains Moser, empirical results usually match the simulated figures to within 10 or 12%.

As stated, you must consider the connector's parameter in the context of the parameters of the board to which it connects. Controlled-impedance board traces imply buried ground planes beneath the signal lines. This requirement poses a special challenge to connector makers: how to effect the interconnect to the buried layers. The high density of many connector systems exacerbates the challenge. Amp's Mictor system, for example, has 25-mil spacing.

Making a right-angle connection to a board edge is the toughest challenge of all. Mictor's designers solved the problem in a clever way. The target board has plated through-holes at its edge, which make contact with the buried ground and power planes. A tool with knife edges cuts slots in the board edge at the locations of the plated through-holes. The ground and power contacts of the right-angle Mictor connector wedge into the slots, and reflow soldering completes the operation.

Multiple-line models are much more complicated than the single-line model in Fig 3. Fig 4, derived from Ref 2, shows the simulated results of modeling Amp's 2-mm Z-Pack right-angle connector. The simulation model is a matrix circuit model that provides for the series resistance and inductance elements of each line and the electromagnetic and electrostatic coupling between lines. This model uses an ECL-level signal with a 500-psec rise time. The electrostatic and electromagnetic crosstalk produce the near- and far-end noise voltages shown in the graphs. The modeling and results become more complex when an inverted signal also exists, giving rise to differential noise voltages.

As stated earlier, any connector-system design must take into account what's connected to it. Ref 3 explains that the effective operating impedance of a backplane loaded with vias, connector pins, module stubs, and driver/receiver devices is much lower than the raw characteristic impedance of the backplane material. The effective impedance seen at any point along the bus is a strong function of the capacitive loading of the module stubs, connector pins, and drivers and receivers. So it's eminently obvious that you can't blithely consider a connector as an isolated component for easy design-in.

Testing is no piece of cake

Testing the characteristics of a connector system in a high-speed digital design is a very complex and specialized art. As an example, consider the crosstalk-test system in Fig 5, which is derived from Ref 4. This is the system used to characterize Augat's EII (electronically invisible interconnect) connector system. The test first used a 500-mV p-p input pulse with 900-psec rise time and 100-MHz repetition rate. The measurement uses a Hewlett-Packard TDR oscilloscope.

Additional tests used the 200-mV step pulse of the TDR scope as the input. A 10-ft length of coaxial cable at the TDR output served to slow the rise time of the step pulse from 35 to 267 psec. The results showed near- and far-end crosstalk at via and SMA-connector locations between 0.8 and 13.9 mV. To underscore the complexity of connector measurements, Ref 4 states that the via holes are an integral part of the measuring system, so it's not possible to determine the exact connector-contributed crosstalk. The important point here is that any meaningful connector measurements must take account of the connector's interaction with the host system.

TDR also serves to characterize impedance discontinuities and resulting reflections. Winchester Electronics, for example, uses the technique to measure reflections in its HD Plus connection system, developed in conjunction with Teradyne Connection Systems Division. Three versions of this connector system, HD Plus, HD Plus One, and HD Plus Two, are available. The One and Two versions provide additional rows of contacts used as low-impedance ground returns. The additional contacts also provide effective electromagnetic shielding. Fig 6 from Ref 5 shows the reduction in reflections stemming from the additional grounding. Note also that the HD Plus system doesn't address only small-signal issues; it also provides hefty 20A/contact power and return connections.

Teradyne, in collaboration with Winchester and connector customers, makes extensive use of Spice modeling to characterize its connector systems. Ref 6 delineates three levels of modeling: Type I models are single-line simulations representing delay and reflection characteristics for a single given signal line in a connector system with a preassigned ground pattern. These models yield no crosstalk-coupling effects. Type II simulations are multiple-line models that add crosstalk-coupling effects but still assume preassigned signal and ground-return patterns. Type III models include all interactions within a large group of pins. Type I and II models might use 10 to 100 lines of Spice description; Type III models commonly run to thousands of lines.

As a final example of the testing challenge, consider the tests performed on Robinson Nugent's Metpak 2 backplane-connection system, as reported in Refs 7 and 8. R-N's testing technique also uses TDR methods—in this case, a Tektronix 11801B TDR scope with SD-24 TDR/sampling heads. The tests cover connector single-ended and differential impedance, propagation delay, and single- and multiple-source crosstalk. Fig 7 underscores a point made earlier: the nonlinear aspects of connector performance with respect to edge speed. The connector displays relatively well-behaved impedance characteristics with a leisurely signal rise time of 1 nsec but suffers an abrupt discontinuity with a blazing 25-psec rise time.

Backplanes are not the only interconnection systems to pose design challenges. High-speed LANs have special requirements for crosstalk, attenuation, and return loss. Thomas & Betts, for example, specializes in the design of connector and cabling systems for these demanding applications. The T&B ALL-LAN interconnection system uses individually foil-wrapped conductors to minimize crosstalk and return loss. The spec sheets for the ALL-LAN system provide curves for near-end crosstalk, attenuation, and return loss for frequencies as high as 300 MHz.

Designing an interconnection system into a high-speed digital system is a complicated and daunting task. You need special skills to understand all of the interactions between the connectors and the system. You also need very specialized expertise to simulate, characterize, and test interconnection systems. In many cases, you'd do well to enter into a collaborative effort with a connector manufacturer, a third-party consultant company, or both.

You can contact Bill Travis by phone at (617) 558-4471, by fax at (617) 558- 4470, or by Internet at b.travis@cahners.com.

References

1. Rambus Channel Design Guide, 1994, Rambus Inc, pg 52 to 53.
2. Electrical Performance Report No. 65722, September 1993, Amp Inc, pg 1, 4.
3. Collins, Hansel and Edward Sayre, "Bussed Clock Architectures for High-Performance Robust ATM Design Applications," (presented at the High-Performance System Design Conference), 1994, Northeast Systems Associates, pg 7.
4. Turcotte, Tammy and Muti Siddiqi, "Preliminary Electrical Test Report for EII," Augat Inc, pg 22 to 23.
5. Perugini, Michael, "HD Plus: A Modular High Density Pin and Socket Interconnection System," Winchester Electronics, pg 7.
6. Gailus, Mark, Mary Ann Fusi, and Fabrizio Zanella, "Electrical Two and Three Dimensional Modelling of High-Speed Board to Board Interconnections," Teradyne Inc, pg 2.
7. Barr, Alexander and Kevin Oursler, "Metpak 2 Connector Electrical Characterization Report," Robinson Nugent.
8. Barr, Alexander and Kevin Oursler, "Inverse Metpak 2 Connector Electrical Characterization Report," Robinson Nugent.