Design Ideas: October 26,, 1995

The circuit in Fig 1a generates repetitive system resets to 68XXX processors. These resets allow you to troubleshoot power-up problems using a scope instead of a logic analyzer or storage scope. This reset card, which you can build for less than $10, consists of a DIP switch, a resistor module, and an AMD MACH210 complex PLD (CPLD).

The switch settings allow you to set the time delay between resets, enabling you to loop on and observe only the first few power-up processor operations or as many as you want. The resistor module pulls up the outputs of the switches. The CPLD generates the reset to the processor. The device contains two counters and a comparator. The first counter, the reset-time counter, determines the length of time that the reset signal will stay low. (You typically find this time in the processor's data book.) The reset-time counter also acts as a count-enable to the second counter, the bit counter. The comparator compares the output of the bit counter to the external switch settings. The output of the comparator determines the delay between resets (Fig 1b). You can download ABEL, JEDEC, and document files for the device from EDN BBS /DI_SIG #1783.

There are only four connections from the reset card to the 68XXX processor: ground, 5V, the RESETC signal, and the clock. You can use regular test clips for these connections. You can use any clock source, as long as its frequency is greater than the processor clock. You can also use this circuit for other processors with little or no modifications to the reset-time counter. (DI #1783)