Design Feature: November 9, 1995

High-speed, high-performance CMOS and BiCMOS ADCs are proliferating in mainstream electronic-system-design applications. Design engineers need a good understanding of the implications of working with these somewhat-esoteric and little-understood devices. Take advantage of the numerous textbooks and seminars now available; they adequately expound on electrical-specification issues and high-speed layout techniques that produce optimum performance. However, the area of total power dissipation is a subject the industry has not thoroughly or consistently documented.

Accurate and total ADC power-dissipation analysis is a prime concern for system applications that require multiple high-speed ADCs or battery operation, as well as for applications with limited heat-dissipation resources. In addition, designers should consider the “green” movement’s mandate that electronic designs should be fully characterized, if not optimized, for maximum power efficiency.

Most manufacturers apply the high-or video-speed label to ADCs whose sampling rates exceed 10M samples/sec. High-performance ADCs are a subset of this group of devices that provide a relatively high level of dynamic performance over a wide analog-input bandwidth. The data sheets of these high-performance ADCs thoroughly describe the devices’ ac performance by containing a full complement of characterized, guaranteed, and tested distortion specifications up to (at least) Nyquist analog-input conditions of A_IN approaching clock/2. Thus, this rather elite group of ADCs endeavors to deliver both high sampling speeds and high ac performance. Such performance demands an appropriate IC fabrication process that can deliver the high drive currents required for fast signal rise times and low wideband distortion.

Depending on its architecture, the performance of an ADC characterized within the range of 10 to 100M samples/sec can vary widely with sample rate, analog-input frequency, and digital-output load conditions. Manufacturers can fabricate these high-speed, high-performance ADCs on a CMOS, BiCMOS, or bipolar IC process technology. Each process yields different power-dissipation characteristics.

Table 1 provides a summary of the array of available ADC processes, their general Nyquist-performance capabilities, and the sensitivity of power dissipation to operating conditions. A bipolar ADC has a saturated logic-type of architecture with a TTL output stage. Thus, bipolar ADCs exhibit virtually no variations in total power dissipation with changes in output load, sampling rate, or analog-input frequency. In a BiCMOS ADC, the input conditioning and encoder stages are generally bipolar, and the digital-output stage is generally CMOS. Therefore, the power dissipation of BiCMOS ADCs exhibits some degree of variability with changing operating conditions. Pure CMOS ADCs present the most extreme case of variability in power dissipation. However, the wideband dynamic performance of currently available CMOS ADCs is not comparable to that of bipolar or BiCMOS converters with sampling rates of 50 to 100M samples/sec.

Aside from process, the popular high-speed ADC architectures of flash, subranging, flash-folding, and sequential SAR also have their own power-dissipation peculiarities. Except in pure CMOS designs, the basic conversion circuitry does not constitute a major element in the relationship between power dissipation and operating conditions. The one exception is the dissipation of the flash converter’s reference resistor ladder. Most high-speed flash-ADC data sheets separately specify the power-dissipation numbers for the reference ladder and the encoder circuitry. Thus, you need to add these two numbers to arrive at the total power dissipation for the ADC.

For example, the Analog Devices AD9002, an 8-bit, 150M-sample/sec flash ADC, specifies a nominal encoder power dissipation of 750 mW and a reference-ladder power dissipation of 50 mW. Although the reference-ladder element of the AD9002’s overall power dissipation doesn’t come from the device’s supply current, the ADC must dissipate this power, and, as a result, you must include it in the device’s thermal analysis. So, in this case, the combined total power dissipation for the AD9002 is 800 mW. Because the reference voltage of the internal ladder is generally a dc level, you can use Ohm’s law to calculate the ladder’s power dissipation. The power dissipation associated with the reference ladder is constant and independent of the ADC’s switching rate or other operating conditions.

The CMOS digital-output stage is the circuit element you must thoroughly analyze when determining the expected power dissipation of an ADC operating in a high-speed application. A CMOS digital-output stage causes such a highly proportional relationship between switching speed and power dissipation because of the stage’s wide output swing. The swing is 0 to a typically 5V supply. Thus, the energy required to quickly charge and discharge the total effective load capacitance is higher than that of any other logic family.

Sources of both internal and external capacitance contribute to the effective total load, and you need to consider their sum. The diode junctions, transistors, and metal and polysilicon interconnects of the CMOS-IC device structure generate internal parasitic-capacitance elements. These internal capacitance sources have the same effect on the ADC’s power dissipation, although usually smaller in magnitude, as the external load capacitances attached to the device’s output pins. ADC data sheets that specify power dissipation include internal (but not always external) sources of output-stage parasitic capacitance as a component of the total power-dissipation figure. If the output stage is switching, the internal capacitance results in power dissipation in the ADC’s output stage, even if no external load is present. The internal output-stage capacitance is a fixed value. However, external capacitance varies, and you can calculate and control this source of capacitance.

Figure 1 shows the structure of a basic CMOS output stage. This circuit uses the V_CC voltage as the logic “1’’ level, which provides a low source impedance, through a MOS device, to charge the combination of the internal- and output-load capacitances directly. ADCs that provide separate supply pins for the digital CMOS output stage are becoming increasingly popular. (The pins are isolated from the supply pins of the encoder stage.) This arrangement allows the user to effectively set the converter’s output logic-level compatibility. Reducing the logic output swing below CMOS logic levels offers the advantage of reducing overall power dissipation in the converter.

Power dissipation within the CMOS output stage is directly proportional to switching speed. During the initial charge phase, the entire supply voltage effectively drops across the MOS device. The resulting current flow produces a period of increased power dissipation within the stage. Obviously, the frequency of the charge/discharge cycle, which the ADC clock frequency and analog input signal determine, will affect power dissipation in addition to the total load capacitance. As previously mentioned, the sum of the internal- and external-load capacitance sources determines the required charging current. The following formula yields the sum of the energy dissipated in a converter due to external capacitance—assuming all digital outputs are driving the same capacitive load and switching at one-half the clock rate and the supply voltage is 5V:

where [sigma]C equals the sum of the load capacitance of all output stages, and V equals the supply voltage.

To calculate the power dissipation of a BiCMOS ADC, consider several factors: output load, sampling rate, output-logic-level voltage, and the switching speed of the analog input. Each of these elements and combinations thereof have a pronounced effect on the total power dissipated within the device. Worst-case conditions for an ADC exist at maximum sampling rate with an analog input of maximum frequency and amplitude and with a maximum external capacitive-load condition. Any variation of these conditions reduces total power dissipation.

To add to the confusion, an increasing number of ADC vendors don’t consider the portion of power dissipation directly attributable to external output-load capacitance and switching speed a true source of dissipation. Thus, these vendors do not include this number in the device’s power-dissipation specification. The accepted convention is that this source of power dissipation is a constant dictated by the laws of physics and is a fixed factor in the application of all CMOS and BiCMOS ADCs. The ADC user, according to the convention, is aware of this source of power dissipation and is interested only in the additional power-dissipation contribution from the internal converter stage, not the CMOS output stage.

This view of the output-stage power-dissipation contribution places the responsibility on the ADC user to understand and anticipate this additional source of power dissipation. System designers are not always aware of this assumption and are frequently—and unpleasantly—surprised by the actual-vs-anticipated ADC power-dissipation measurements.

The following example shows how to analyze an ADC operating at various switching speeds with a diverse range of output-loading conditions to arrive at a real-world operating-power-dissipation figure. This example uses the Analog Devices AD9050 ADC, which is a relatively low-power, high-performance, 10-bit, 40M-sample/sec device. This ADC delivers an S/N ratio of 56 dB at an analog-input frequency of 10.3 MHz with a 40M-sample/sec clock. The BiCMOS ADC has a CMOS output stage, and the T/H amplifier and encoder circuitry are bipolar. The AD9050’s data sheet specifies a power dissipation of 340 mW with a 40M-sample/sec clock operating on a single 5V supply.

The goal of the first part of the benchtop analysis is to characterize the individual elements of power dissipation within the AD9050, operating under varying conditions, to reveal a complete picture of its power-dissipation source. The first test measures power dissipation with the ADC operating in a best-case condition: a nominal bit-output load capacitance of 5 pF, a conversion clock of 5 MHz, and a static dc analog input. These conditions result in no output bits switching. Thus, the power dissipation is that of the encoder stages, alone, without any contribution from the CMOS output stage. Under these conditions, the ADC dissipates 272 mW, which represents its minimum power-dissipation condition in a realistic system application.

The next part of the analysis consists of collecting data points while sweeping the encode clock over the range of 5 to 40 MHz with a static-analog input. Figure 2 shows the results. Under these static-input conditions, total power dissipation varies from 272 to 310 mW, which represents a 14% change in power dissipation. This element of the ADC’s power dissipation is attributable to frequency-sensitive internal CMOS clock-drive circuitry.

Figure 2 also shows the results with the same output-load conditions and encode-clock frequency range but with a 20-MHz full-scale analog-input signal. This input causes all output bits to switch at one-half the clock rate, which is the maximum dynamic condition. With this 20-MHz input, the ADC’s power dissipation varies from 277 to 340 mW across the 5- to 40-MHz clock range, which is a 23% overall change. You can attribute this dynamic element of power dissipation to the CMOS output stage’s driving the nominal 5-pF load across the maximum operating frequency and output-bit switching conditions. The calculated value for the power dissipation in the CMOS output stage at the 5M-sample/sec clock rate (with dynamic input, per the given formula, where C=5 pF and V=5V) is 0.3 mW/bit, or 3 mW total for the 10-bit converter. At the 40M-sample/sec rate, the value is 2.5 mW/bit, or 25 mW for the total ADC.

Figure 3 shows the results of increasing the external capacitive load to 20 pF, which simulates a heavy digital-output load. The encode rate varies over the same 5M- to 40M-sample/sec range; Figure 3 includes separate plots for static dc and dynamic ac analog-input conditions. The dc plot shows power dissipation ranging from 272 to 310 mW—the same as for the 5-pF output load, as expected. The ac-input plot shows power dissipation ranging from 284 to 416 mW. Again, as a comparison, the calculated value for the power dissipation at the 5M-sample/sec clock rate with maximum dynamic input for this output load is 1.2 mW per bit, or 12 mW total for the ADC. At the 40M-sample/sec rate, the value is 10 mW per bit, or 100 mW for the total ADC.

This analysis reveals that moving from best- to worst-case operating conditions results in AD9050 power-dissipation measurements that range from 272 to 416 mW. This 53% variability in power dissipation over this not-unreasonable set of operating conditions is a direct result of this ADC’s CMOS output stage. Obviously, this variability should be a significant consideration in system thermal analysis. The AD9050’s data sheet does include curves of power dissipation vs various clock rates and analog-input conditions to better represent its total power-dissipation characteristics to the user.

Using the model in Figure 4 helps you evaluate a given high-speed-ADC application’s expected power dissipation for a given set of operating conditions. Performing this type of preliminary power-dissipation analysis should help you avoid problems such as lower-than-expected system battery life and premature component failure resulting from excessive temperature rise.

1. Motorola High-Speed Logic Databook, 1983.