Design Ideas: November 9, 1995

Many applications require high-resolution, multichannel, large-bandwidth signal acquisition. Some examples are vibration analysis, vehicle telemetry, and telecommunications. You could use an array of A/D converters to address such applications, but ADCs are costly and consume considerable board space. Figure 1 shows a complete and cost-effective, high-speed, differential, eight-channel, 12-bit acquisition system that uses few parts.

IC₁ and IC₂ are the multiplexers for IC₃’s +A_IN and –A_IN analog inputs, respectively. IC₁ and IC₂ share the chip-select-multiplexer, serial-data, and serial-clock lines. This configuration selects the same channel on each multiplexer: S0 for both +CH0 and –CH0, S1 for both +CH1 and –CH1, and so on. If you select a new channel pair for each conversion, the system’s sampling rate is 78k samples/sec, with an input-signal bandwidth of 39 kHz. If you use the same channel pair for consecutive conversions, the circuit makes full use of IC₃’s 1.25M-sample/sec conversion rate.

The timing diagram in Figure 2 shows that the circuit pipelines the multiplexer-channel selection and A/D conversion to maximize system throughput. The conversion begins by selecting the desired multiplexer-channel pair. With logic high applied to the CS input of IC₁ and IC₂, the channel-pair data clocks into each DATA1 input on the rising edge of the 5-MHz clock signal. Chip-select multiplexer then goes low 700 nsec before IC₃’s conversion-start input, CONVST*, switches low. This timing allows for the multiplexer-channel turn-on time of IC₁ and IC₂, thus ensuring that the input signals fully settle before IC₃’s S/H amplifier captures the signal.

IC₃’s S/H amplifier acquires the input signal, and the A/D converter begins the conversion on CONVST’s* falling edge. During the conversion, the CS inputs of IC₁ and IC₂ go high, and the data for the next channel pair clocks into DATA1. The pipelined operation continues until the completion of a conversion sequence. (DI #1790)