EDN Magazine -- 11.09.95 alculating power dissipation of high-performance ADCs table 1

**TABLE 1 ADC FABRICATION PROCESS VS POWER-DISSIPATION SENSITIVITY**
ADC fabrication process	Output logic	M-sample/sec range	Power-dissipation sensitivity to operating conditions
Bipolar	TTL	10 to 100	None
Bipolar	ECL	10 to 500	None
BiCMOS	TTL	10 to 100	None
BiCMOS	ECL	10 to 500	None
BiCMOS	CMOS	10 to 100	Medium
CMOS	CMOS	10 to 75	High
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