Design Ideas: November 23, 1995

When a PC-driven solid-state or electromechanical relay controls external equipment, take care to design an interface that avoids false triggering. The interface circuit in Figure 1a switches the relay on and off only after a specific sequence of outputs. Thus, this design protects the relay against the influence of computer-reset and I/O operations that some drivers perform during system start-up to locate add-on cards.

The GAL20V8 PLD occupies four locations in I/O address space and integrates the address decoder, state machine, and feedback path. You can preset the address decoder to one of four base addresses (300, 320, 340, or 3E0 hex) for easy remapping. The state machine uses the I/O write strobe (IOW) as the clock, so that only outputs determine the controller's behavior. Figure 1b's state diagram shows that any incorrect step in the access sequence causes the controller to return to idle state, S3, which is also the power-up state. The feedback path allows the design to inspect the controller state and confirm the relay's operation; the design pulls the CHK pin high when the relay is off and ties CHK to ground through contacts when the relay is on. The optional buzzer in Figure 1a provides additional audible confirmation; if not required, you can replace it with a pullup resistor.

By accessing EDN's bulletin-board system, you can download the C source and executable code and PAL listings from EDN BBS /DI_SIG #1792 (dial (617) 558-4241, 300/1200/2400, 8, N, 1). Some system programs override interrupt control. Therefore, in spite of disabling interrupts, the access sequence repeats several times. With this repetition, the design can successfully switch the relay even if previous attempts failed because of an interrupt handler's I/O activity. (DI #1792)