Out in Front: November 23, 1995

Iddq testing, an approach aimed at lowering the cost of IC test, was the subject of a day-long workshop sponsored by the IEEE in conjunction with the International Test Conference (ITC) in Washington, DC, in October. Iddq testing uses a CMOS IC's supply current, IDDQ, as a measure of chip defects. The technique is effective for detecting bridging faults (shorts between metal layers) that are increasingly common in chips with submicron feature sizes. Many bridging faults are undetectable with test techniques based on the more traditional "stuck-at" fault model.

The workshop papers suggest that some early proponents of Iddq testing were too optimistic. Iddq testing, though often cost-effective, is rarely free. As chips grow in complexity, they frequently require special features to implement Iddq tests. IC manufacturers also worry that Iddq causes the rejection of good devices. However, Tony Miller of Intel in Chandler, AZ, Jerry Soden of Sandia Laboratories in Albuquerque, NM, and Chuck Hawkins of the University of New Mexico, Albuquerque, refuted this point. Moreover, despite the availability of automatic test-pattern-generation (ATPG) tools that generate Iddq vectors, further tool refinements appear necessary.

Major problems with Iddq have been the difficulty of measuring minuscule supply currents and the time required for the current to settle to a quiescent state. A paper by Adit Singh of Auburn University, Auburn, AL, suggests that you can obtain useful results without waiting for settling. Another paper, by Josep Rius and J Figueras of Universitat Politechnica de Catalunya in Barcelona, Spain, suggests that current measurements may sometimes be unnecessary. You can remove power from the device under test and monitor the voltage decay on the power-supply decoupling capacitor while applying a sequence of test vectors to the IC inputs. This technique sometimes gives you data you seek.

This approach, unlike the technique that Keating and Meyer proposed at ITC in 1987, does not require cycling of the device power. Attendees questions indicated that they immediately thought of refinements to the proposed approach. For example, instead of basing a pass/fail decision on a single voltage measurement at a specific time after removal of device power, you might measure how much VDD changes upon application of each vector. This technique might provide a much more sensitive indication of IC quality.

You can purchase the workshop proceedings from the IEEE Computer Society Press.
-- by Dan Strassberg

IEEE Computer Society Press, Los Alamitos, CA, (714) 821-8380.