Out in Front: November 23, 1995
Arcadia, a new extraction tool from Epic Design Technology, accurately extracts RC-equivalent circuits of submicron-chip interconnect lines. This ability is critical for the design of such chips, because interconnections be- tween transistors in 0.5-mm and smaller circuits cause circuit delays that dominate total design delays. Arcadia lets you do extractions on an entire chip or on selected nets of interest, such as clock lines or critical propagation paths.
For accurate net extraction on submicron devices, electronic-design-automation tools apply 3-D field-solving algorithms. These algorithms determine electric fields around and current flow through interconnect lines, giving you precise resistance and capacitance values. Field solvers are accurate but slow. Arcadia avoids the problem of slow runtimes by performing a ̉quasi-3-D" extraction for capacitance, looking at the front and side views of an interconnect structure and combining the results. Epic claims that Arcadia's extraction runs 10 to 20 times faster than and achieves 10 to 20% the accuracy of 3-D field solvers. For resistance extraction, Arcadia uses field-solver extraction and ̉learns" as it runs. When it encounters a structure that is not in its library of recognized patterns, it adds that structure to the library. The next time Arcadia finds the same geometry, the tool brings that structure up, saving analysis time. Arcadia has two capacitance extractors, letting you choose different levels of analysis for different situations. For full-chip extraction, you choose the quasi-3-D capacitance extraction for faster runtime. For a selected net or cell, you select the field-solver capacitance extractor with its higher accuracy but lower speed. Capacitance analysis with field extraction, like resistance, uses the library of recognized patterns to reduce extraction time.
You input information to Arcadia as process information, such as metal-interconnect thickness, oxide thickness be- tween metal layers, and contact and via resistance. Arcadia combines this information with data in the design's layout-vs-schematic (LVS) file. Arcadia uses the combined data to create an Arcadia Technology File, which is the basis of all of the tool's calculations. Using the netlist notation from the LVS file, Arcadia then guarantees correct name mapping for back-annotation of parasitic RC values into the netlist. The tool generates Spice and standard-parasitic-format (SPF) files, which you then input into timing and other analysis tools. Arcadia also has a graphical viewer, which lets you view selected nets that you have extracted. You can highlight selected nets, blocks, or cells, including their parasitic RC values. You can also highlight entire clock-distribution networks for your chip. Arcadia runs on Hewlett-Packard, IBM, and SPARC workstations. Prices start at $20,320.
-- by Jim Lipman
Epic Design Technology, Santa Clara, CA. (408) 988-2997.