Signals & Noise: December 7, 1995

Going hands on

Your article “PCI: Real Versus Ideal” (EDN, Oct 26, 1995, pg 59) was enlightening and informative in presenting a number of issues related to PCI performance. From EDN’s pre-issue publicity and advertising, we were led to believe that us this was to be an eye-opening article. However, I had wished that you would have exposed the heartaches, headaches, and terror that many of us experience when designing a PCI card using off-the-shelf FPGAs and CPLDs from numerous sources, such as Xilinx, Actel, QuickLogic, AT&T, and AMD. I have found that most manufacturer’s PCI application notes are hardly ever the solution to a real product design. Also, I had also hoped that your article would provide for a shoot-off between PLX and AMCC chips.

Listing the various PCI Bridge chips available, especially those that are an alternative to Intel’s Triton/Neptune/Saturn PCI chips sets, would have been helpful. There are significant differences in performance that you can expect to see if the PCI bridge is not a Triton. As you mentioned in the article, the Triton chip set offers the highest PCI bus performance to date. The engineers at Intel should be commended for their excellence in developing such a capable and truly superior PCI chip set.

I designed a PCI card that uses a QuickLogic FPGA as the PCI interface. This design let me implement a PCI interface that operates at the full 132-Mbyte/sec burst rate during data-transfer phases; I could also vary the burst sizes up to the maximum latency-timer limit allowed. Our lab measurements showed a sustained transfer rate of 118 Mbytes/sec when we installed the PCI card in a Digital Equipment Celebris GL5100 PC, which uses the Triton chip set with the Pentium.

I have included some PCI-bus master-data-transfer-rate measurements of the chip sets into which I plugged the card. The information should provide some insight into relative performance expected in assorted platforms (see Table 1).

As a final note, one major item in your article concerns a discrepancy between the HP 16500 logic-analyzer waveform (pg 61, Figure 2b) and what you stated on pg 62. You said: “Burst-write performance for the Triton motherboard was even better (Figure 2b). After a one-bus-clock latency, write cycles took place on every bus clock.” The discrepancy is that the waveform in Figure 2b shows the TRDY signal going up and down during the burst cycle. This definitely means that wait states are being added during the burst, and write cycles could not have possibly occurred on every bus cycle. For your text description to be correct, TRDY should have been asserted low during the entire burst. Somehow TRDY did not appear on the picture correctly.

Because a certain amount of your credibility is at stake here, it would be nice if this discrepancy is cleared up for your unsuspecting readers. I look forward to your follow-up articles on PCI-bus designs. Thanks for providing such timely and valuable information to us all. Your magazine and its articles are so valuable to engineers. I have always believed that EDN should be considered a national treasure.

Brian Koga
Concept Development Inc
briank@cdvinc.com