Design Feature: December 7, 1995

As you deal with increasingly high frequencies and tightened design dimensions, such as those found in multichip modules (MCMs), signal integrity becomes a more critical and widespread concern. Fortunately, you have access to powerful signal-integrity EDA capabilities from several vendors. By understanding the nature of these capabilities, you can make informed decisions about what types of capabilities are useful in specific situations. You can also learn to identify and eliminate potential signal-integrity problems and whether a particular EDA tool applies to your design by knowing the frequency range over which a problem can occur.

The most prevalent signal-integrity problem is signal distortion, a deviation from an ideal logic signal. Although few, if any, logic signals are ideal, distortion becomes a subject of concern when it threatens to change system operation or damage components. Distortion effects include signal undershoot and overshoot, ringing, and unintentional crossings of logic thresholds.

These distortions are most troublesome when they occur on a device’s clock inputs, where small signal deviations can cause false or multiple clocking. Distortions can also cause problems on device inputs. For example, distortions such as ringing can cause a data signal to be at a logic level different from where the signal should be at the time a circuit is clocked. Furthermore, too much undershoot can violate the specifications for some nonclock inputs, leading to device failure.

Most signal distortions result from reflections. A fast-rising signal propagates down a pc-board trace like a wave, with part of the wave reflecting from the trace’s endpoints and discontinuities, such as connectors. The reflections then re-reflect from other endpoints and discontinuities in the net. These reflected voltages add to or subtract from “outgoing” signals, changing the shape of the waveform and thus causing distortions.

Reflections become a problem when the round-trip transition time from driver to load and back to driver is less than the driver’s rise time. Reflections generally cause problems in logic circuits at frequencies higher than 25 MHz for typical pc-board and MCM designs. Assuming a 2-nsec/ft propagation velocity and a driver that has a 1-nsec rise time, a net longer than 3 in. would experience problems. Table 1 lists typical values for specific logic families.

At higher frequencies and with smaller geometries, factors such as conductor skin-effect resistance and dielectric losses can cause signal distortion, which leads to excessive signal delay. Smaller diameter conductors, such as those on MCMs, exhibit these effects at lower frequencies. Ohmic loss can also contribute to signal delay due to distortion and is a frequency-independent function of the materials used in the MCM or pc board.

The traditional way of handling signal-distortion problems is to terminate lines so that they reduce reflected voltage. Unfortunately, the cleanest signal is not necessarily either the fastest signal or the one with lowest power dissipation.

If you apply conservative termination strategies throughout your logic, you can avoid most distortion problems. You might also unnecessarily hobble your logic, however, slowing the system and increasing power consumption to bypass potential signal-distortion problems. To avoid this trap, you could skimp on terminations and plan to correct the problems that arise in debugging your prototype. The danger of this time-consuming approach becomes apparent when component tolerances lead to problems that did not occur in your prototype but emerge in your production systems. You can avoid both of these extremes by using signal-integrity tools. These tools can tell you which specific nets will suffer from distortion problems, so that you can make intelligent design trade-offs. Your system can be clean and fast and consume a minimum of power, as well.

Coupling between signals, or crosstalk, is another source of signal distortion, which occurs when signal voltages in one conductor induce currents in adjoining conductors (capacitive coupling) or when signal currents induce voltages in adjoining conductors (inductive coupling). Capacitive and inductive coupling work together to distort signals and, as with other forms of signal distortion, can lead to corrupted data and false clocking. Crosstalk can cause these problems over a wide range of driver rise and fall times, signal frequencies, and separations between pc-board and MCM traces.

The most obvious ways to lower potential crosstalk are to increase the distance between pc-board traces, add guard traces, or route signals onto different pc-board layers. These methods can increase signal delay, however, and, possibly, system size as well. You can reduce crosstalk by avoiding parallel traces, but that is not always practical, especially on backplanes. You can reduce crosstalk by avoiding the use of microstrip traces, but this method requires that you give up the fastest structure available. Using devices with lower slew rates also reduces crosstalk but leads to a slower system. The only logical way to make these and other crosstalk trade-offs is to get specific information about crosstalk problems in your design. Then you can add space only between problem traces or slow a problem net only when it is not in the critical path. This approach eliminates crosstalk and maintains the highest viable system speed and density.

One way of looking at increases in logic speeds is to note that, because the delays through logic devices are becoming shorter, the delays between devices represent an increasingly large portion of overall cycle time. Even at 25 to 40 MHz, interconnect delays account for 30% or more of critical-path delays. This figure can be as high as 70% in some of today’s high-speed systems. To correctly simulate a high-speed logic circuit’s behavior, you must include realistic information about the circuit’s interconnect delays.

The propagation delay of a conductor depends on the length of the conductor and the effective speed of light in the insulator surrounding it. This relationship indicates that interconnect delays in pc-board traces stem from the trace’s length and from properties of the board’s dielectric. When traces are short or connect to a highly capacitive load, the interconnect delay depends less on propagation time than on the time for a driver to charge the trace’s capacitance.

Increasing a trace’s length to reduce crosstalk increases interconnect delays. In addition, choosing a board material that reduces signal delay increases the likelihood of signal distortion and crosstalk, but terminating a line to reduce signal distortion increases propagation delay. In short, signal distortion, crosstalk, and interconnect delay are closely related. Only by getting specific information about your design’s characteristics can you make the best trade-offs; signal-integrity EDA tools can help in this area.

EMI becomes a problem when a logic circuit radiates energy beyond the system’s boundaries. The problem can be especially troublesome when the EMI violates FCC regulations. Designers usually solve this problem by adding shielding, but you can often more economically reduce EMI by modifying the offending logic.

By using a signal-integrity tool that calculates the EMI a piece of logic generates, you can pinpoint nets that are responsible for most of the emissions. You can often change these nets so that they generate lower EMI levels without impairing your design’s performance. A little extra design work can reduce the amount of required shielding and save money on the final system.

Instead of fixing problems at the end of the design cycle, signal-integrity EDA tools allow you to prevent problems in earlier phases of your design. Even before you move a design into the place-and-route phase, you can do a what-if analysis of critical nets. Estimates of wire length and bus loading let you quickly find the constraints for these nets. You can then feed this information into placement tools to avoid trouble. What-if analyses can help you configure your design’s topology, loading, powering, and termination. In software, you can prototype critical networks, such as clock distribution and memory-address and video lines.

Signal-integrity tools can also be useful after the initial placement of components. You need a preliminary routing for this placement, including features such as evenly distributed clock trees, to know which branches and wiring layers may contribute to signal-integrity problems. With this rough layout and information about the implementation method (pc-board materials, for example), the tools can perform more refined what-if calculations of signal distortion and interconnection delay. This information can help avoid problems in the routing phase by analyzing factors such as topology variations, termination strategies, and bus contention. For example, the tools let you see whether differential drivers make sense for a given application. You might find, in some instances, that you are overdriving a line.

For what-if calculations of interconnect delay, signal-integrity tools provide more accurate results than do simulators, which treat delay as a simple capacitive-loading function. Signal-integrity tools work with complex functions of driver characteristics, line length, line loading, and pc-board physical characteristics. Finally, you can use signal-integrity tools for a back-end analysis of your layout to ensure that your design is “clean” before spending money on prototypes. Feeding interconnect-delay information into a timing verifier or simulator provides accurate data on your design’s behavior.

Because interconnects contribute as much as 70% of the overall cycle time in some circuits, timing verifiers and simulators must have information from signal-integrity tools to provide accurate results. That information not only provides better accuracy, but also reveals some surprises about your design, such as identifying critical nets that you did not know were critical.

Well-established signal-integrity tools are available for use on pc boards and cable/connector components. These tools also work well for MCMs, which the tools treat as small pc boards, and for backplanes, which the tools treat as combinations of connectors and pc boards. Additionally, tools are now pushing down into the realm of the IC and up to encompass entire systems. Modeling ribbon-cable assemblies is fairly straightforward, but creating the models for arbitrary cable assemblies can require much manual information entry. In return, however, you get information about the way signals on the cable will behave, although you can obtain accurate delay information about a cable just by knowing its length.

To understand what signal-integrity tools can do for your designs, it is useful to understand how these tools work and what information they provide. The requirement for a signal-distortion tool is simple: It must perform automatic transmission-line analyses of each net of interest. This seemingly simple task demands highly sophisticated computation, because the tool must calculate the effects of arbitrarily complex nets, both linear and nonlinear circuit elements, and impedance discontinuities caused by vias and connectors. The tool must do this for an entire pc board in a time span that does not place too much burden on human patience. The tool should also be able to exchange information with other EDA tools, which are performing tasks such as placement, routing, timing verification, and simulation, and operate on the same platforms as these tools.

Fortunately, today’s EDA tools are equal to the task, and the results are straightforward, including predictions of ringing, undershoot, and overshoot, as well as accurate delay information. In addition to feeding this information into timing verifiers and simulators, a signal-distortion tool can show you calculated waveforms. For sufficient accuracy, a tool should solve—not just emulate—transmission-line equations. Accurate transmission-line parameters, including inductance, capacitance, mutual inductance, and mutual capacitance, are essential. Only an electromagnetic-field technique can accurately generate such parameters.

To arrive at useful results in a reasonable time, signal-integrity tools, whenever possible, use behavioral models for digital devices instead of traditional Spice circuit-level models. For mixed-signal designs, you need more comprehensive driver modeling. The best tools support both types of simulation and use a direct-solution transmission-line model. Tools treat a net as a combination of segments, straight portions of traces, vias, and so on, so that each segment can have different properties. Combining the trace-segment models with driver and load models results in a complete model for the net. To further simplify calculations, some signal-integrity tools ignore ohmic and frequency-dependent losses in conductors. This simplification can result in a serious loss of accuracy in high-speed designs. Signal-integrity tools also can include Monte Carlo simulation and the ability to generate a Spice-compatible transmission-line connection model of any given net.

As an example of how a signal-integrity tool allows you to evaluate signal distortion, consider an analysis of an ECL clock network (Figure 1). To do the analysis, the tool requires information about the driver, the topology of the trace, including branches or forks, and loads, such as vias or receivers. The information on the trace includes the trace velocity and impedance, although most tools provide default values for these parameters. The tools also allow you to set voltage-threshold values for parameters such as logic “high” and “low,” undershoot, overshoot, peak noise, root-sum-square noise, ground bounce, and V_CC bounce. As with other types of simulators, you can set timing values, such as the basic time steps for calculation and for waveform display. Again, most tools supply default values for these parameters that depend on the logic technology involved.

Figure 2 shows the waveforms that result from the tool’s analysis. These waveforms include the voltages seen at various points on the net between R₁ and the output of the driver, including vias, and points at which the trace splits. The dotted horizontal lines on the waveform indicate switching thresholds for the receivers. You can display vertical cursors (dotted and solid lines) on the waveform to measure voltage and time characteristics, as displayed at the bottom of the screen, resulting in a display similar to that of a good digital oscilloscope.

A good signal-integrity tool can also generate a report of waveform parameters, such as rise and fall times and overshoot (Table 2). The tool can also list any exceptions to the threshold values, including overshoot, peak noise, and so on. This capability lets you quickly check for predefined error conditions. A high-performance signal-integrity tool can perform the analysis on the net of Figure 1 in about 1 sec on a SPARC II workstation. The analysis in Table 2 reveals error conditions, indicating that the designer forgot to put a terminator on the net. A signal-integrity tool with a built-in node editor lets you change the net in a single integrated environment.

After adding a 200V terminator tied to –5.2V to the net, rerunning the analysis shows that the waveform (Figure 3) is now acceptable. The sequence of analysis, rework, and reanalysis takes only a few minutes and prevents significant problems in the prototype stage.

Signal-integrity tools that calculate crosstalk use the same inputs as those for calculating signal distortion. The difference between the two calculations is the addition of models and algorithms for coupling between conductors, and the same tool often performs both types of analyses. Because coupling between conductors is mathematically complex, the success of a crosstalk tool depends on the tool’s field-solution algorithms. Traditional methods for calculating these nonlinear fields are too slow for working with an entire pc board or MCM. On the other hand, the algorithms must be highly accurate relative to the sensitivity of the logic technology. The only way to know what you are getting is to test the tool.

The field-solution algorithm must consider the relationships among a pc board’s conductors, grounds, and dielectric. Field-superposition algorithms calculate the electric and magnetic fields; other algorithms then calculate the resulting capacitive and inductive coupling matrices to simulate crosstalk.

Figure 4 illustrates a typical trace configuration for which a tool must calculate crosstalk calculation. Only a small segment of Network B is likely to couple to Network A. The tool must know the nets’ topologies, the pc-board characteristics from the physical layout, and the nature of the signals on the nets. Most of this information comes from your other design tools.

Table 3 analyzes a more difficult crosstalk situation, profiling the traces associated with a bus. In addition to calculating the coupling between adjacent traces, the tool must consider noise that couples across more than one trace for the best accuracy. Complicating the situation further, the crosstalk tool must simulate each possible state of all drivers on all passive nets. This step is necessary because the state and position of the drivers on passive nets determine the amount of noise the drivers absorb. For these reasons, one net might experience 50 to 100 states. Fortunately, information on worst-case crosstalk can let you focus on areas where crosstalk may be a problem. You can apply system timing parameters to define when signals switch and when inputs are sensitive to determine more typical noise values.

To see what a crosstalk simulator reveals, consider the simple configuration shown in Figure 5. Net SL1-A is active, and SL1-P is passive. If you have entered the information to simulate signal distortion, you can specify a crosstalk-proximity window and the necessary crosstalk thresholds. You can then simulate crosstalk. Figure 6 shows the results of the simulation. The glitch at 2 nsec could pose a problem because it crosses the lower switching threshold. The designer must change the net to eliminate this glitch.

Signal-integrity tools provide information on interconnect delay as part of the same procedures that calculate signal distortion and crosstalk. Delay reports list the minimum and maximum switching times from each driver to each receiver. These times depend on interconnect delay, but that delay also depends on the drivers and receivers. Some tools can perform mixed-technology analysis, providing individually specified thresholds for different receivers.

The crucial determination for delay on a net is whether an input node will switch on a signal’s incident wave or require reflections to cross threshold. The tool must calculate the initial wave step and wave-propagation effects based on driver characteristics, line impedance, line velocity, and line length. The tool then determines the driver-to-receiver timing as a function of the calculated waveform and the receiver’s threshold characteristics.

Sometimes, a driver cannot drive a net with enough voltage to switch a receiver solely on the incident wave. In this case, the driver needs the reflected wave as well as the incident wave, effectively doubling the interconnect delay. Feed this information back into your timing verifier or simulator to determine whether the extra delay will cause any problems.

Evaluating pc boards and associated hardware as 2-D structures does not always result in adequate accuracy. Some signal-integrity tools, therefore, offer 3-D capabilities. Structures such as interlayer vias, corners, crossovers, connectors, and package lead frames can contribute significant amounts of circuit parasitics that an EDA program can derive only when it treats such structures as 3-D objects. The 3-D parasitics result from many factors, including via and land (the region allocated for a package pin) diameter or clearance to the ground plane, effects of right-angle traces vs skewed or curved corners, and coupling effects of perpendicular or skewed signal-line crossovers vs signal and ground proximity.

A 3-D signal-integrity tool calculates the self- and mutual-capacitance and inductance of the 3-D structures. The tool extracts these values as lumped-element electrical equivalents, which you use to enhance the accuracy of signal-distortion and crosstalk simulations. With 3-D information, you can rapidly simulate alternative interconnect strategies. When you configure the ground/signal interdigitation in a connector header, for example, getting an early and accurate analysis of how the signals interact can save time later in the design cycle.

Simulating EMI from a pc board or MCM depends on a signal-integrity tool’s ability to calculate high-frequency signal effects. Once a tool predicts accurate waveforms for each net, the tool can predict EMI by propagating the signals and calculating the frequency-dependent electric-field intensities at arbitrary points in space. In this way, the tool simulates open-field EMI tests in which you define ideal antennae, which are noiseless and have infinite bandwidth, around the simulated pc board or MCM. Place the simulated antennae anywhere in space and use them to monitor E-field (in decibels of microvolts per meter) or H-field (in decibels of nanoamperes per meter) intensities in horizontal or vertical polarization or total field strength. Simulated spectrum analyzers attach to the antennae and divide the received signal into its power-spectral components for display.

In an EMI simulation, the tool must assume a time-varying signal pattern on each net. A pseudorandom pattern works for data lines and produces noise with a continuous spectrum. Some tools allow you to improve accuracy by specifying some nets as clock nets, which the tool then simulates with periodic signals. This pattern results in a discrete set of spectral spikes at the fundamental frequency and its harmonics.

To move from net waveforms to the complete open-field simulation, the tool begins by simulating a net and calculating the radiation from each net segment. The tool then sums the radiation over all segments to obtain the radiation from the entire net. Summing the noise power over all nets gives the radiation for an entire board. The tool can then produce a full-board radiation plot, along with a report of each net’s contribution to the total EMI.

Knowing the contribution from each net lets you reduce the effects of major sources of EMI and see how much those reductions, in turn, reduce the overall EMI in subsequent simulations. To reduce EMI, reduce the net’s loop area and check for ground discontinuities.

With accurate data on EMI, signal distortion, crosstalk, and interconnect delay before prototyping, you can make intelligent trade-offs and stay on schedule with your designs. Signal-integrity tools provide much the same information as prototype testing but less expensively and with a better view of worst-case conditions.