Design Ideas: December 7, 1995

When a tachometer is a critical part of overspeed-shutdown circuitry, the response time of conventional demodulators may be too long. The circuit in the block diagram in Figure 1 provides updated speed data. The circuit provides corrections for variations in excitation amplitude and frequency at every excitation half-cycle. The circuit is independent of processors and, therefore, immune to software- and bus-related failures.

The tachometer's output is a sine wave whose amplitude is proportional to excitation and rotational speed. This sine wave's phase is 0 or 180₈, depending on direction. The 115V-ac, 400-Hz tachometer excitation may contain some high-frequency noise as well as common-mode voltage. IC_1A in Figure 2, configured as a differential amplifier with a gain of 1/17.6, rejects the common-mode signal. IC_1A provides the input to IC_1C, a bandpass filter with corner frequencies of 27 and 1100 Hz and a phase shift of 35.68 at 400 Hz. IC_1C provides the reference signal, V_REF.

IC_1B buffers the tachometer's output and drives IC_1D, a bandpass filter that matches the IC_1C filter. The output of IC_1D is the tachometer signal V_TAC. The excitation signal, attenuated by 1/44.5 and phase-shifted by 54.48º, drives the window comparator comprising IC_2A and IC_2B. The comparator's output, V_SH, is a 10-µsec-wide pulse that coincides with the peaks of the sine waves at the outputs of the bandpass filters. This pulse controls two ICs, IC₅ and IC₆, that sample those peaks.

IC₃ converts V_REF to a square wave that drives switches IC_4A and IC_4B. These switches change the S/H circuits from inverting to noninverting every half cycle of the reference signal. This switching eliminates the need for separate absolute-value circuits. IC₇ is a divider that takes the ratio of the S/H outputs. The resulting signal represents the tachometer's shaft speed, corrected for variations in excitation frequency and amplitude. The response time of the circuit is less than 2 msec. The following are some design considerations for the demodulator:

Differential amplifier -- the gain of this stage is chosen to prevent output saturation at the maximum excitation of 176V peak. Tight-tolerance or matched resistors maximize the CMRR.

Buffer -- the high output impedance of the tachometer makes a buffer necessary.

Filters -- lowpass Bessel filters provide minimum response time and good immunity to high-frequency noise. The dc-blocking capacitors eliminate excitation and first-stage offset errors. Resistors of 0.01 and 5% capacitors make the two filters nearly identical.

Phase shifter -- a simple RC network shifts the phase of the excitation 54.4µ and attenuates it to about 3V ac. C₁ must be able to withstand spikes and surges; however, error cancellation by the divider makes 5%-tolerance components adequate.

Window comparator -- with comparison points set at ±100 mV, the window comparator provides a 10-µsec positive pulse at every zero-crossing of the phase shifter's output. The combined phase of the filters and phase shifter is 90º, making the pulse coincide with the peaks of V_REF and V_TAC. Because the slope of a sine wave is very small near the peak, variations in pulse width and location cause negligible errors. The comparator resistors, therefore, need no tighter than 5% tolerance.

S/H -- the AD585 is chosen for its speed and differential input. With the help of IC_4A, IC_4B, R₂₀, and R₂₂, the sample-mode gain switches electronically between +1 and -1. R₁₉ and R₂₁ compensate for the 25[ohm] on-resistance of the DG200.

Comparator -- an LM311 converts V_REF into the reference sign signal, V_RS, with R₁₇ and R₁₈ adding enough hysteresis to prevent oscillations. Because gain switching occurs 90º from sampling, 5% resistors are adequate.

Divider -- because the tachometer can turn in either direction, a two-quadrant divider is necessary; however, the small range of V_REF (±20%) reduces the accuracy requirement. The MPY534 is chosen for its simplicity, accuracy, and response time. (DI #1761)