Out in Front: December 7, 1995

Synopsys has updated its Test Compiler software to speed silicon-chip design-for-test (DFT). Version 3.4a of Test Compiler improves on the current “two-pass” method of test synthesis by combining two of the major design steps—scan insertion and a reoptimization—for inserting scan logic into a chip. When designing chips using a high-level description methodology, adding scan logic after initial simulation can change the chip’s logic, requiring reoptimization with a second synthesis step to assure the chip still meets design specifications. Synopsys estimates the time you take using conventional methods for a 100,000-gate ASIC at one to two hours for a scan and 10 to 20 hours for reoptimization for a Sun SPARC-10 workstation. Test Compiler 3.4a cuts this time to two to three hours for both steps using “constraint-optimized scan insertion,” a one-pass test-synthesis design step. After you have an optimized, testable design, the product lets you create automatic-test-pattern-generation (ATPG) and fault-simulation vectors.

Two versions of Test Compiler 3.4a will be available in the first quarter of 1996. Test Compiler, which provides full- and boundary-scan insertion and testability-rule checking, costs $50,000. Test Compiler Plus, which has all the features of Test Compiler and adds partial-scan insertion and sequential-ATPG capabilities, costs $95,000. Both versions run on Unix workstations. -- by Jim Lipman

Synopsys, Mountain View, CA. (415) 962-5000.