Out in Front: December 7, 1995

LSI Logic’s new Iddalyzer automated design-for-test (DFT) methodology for ASICs complements existing chip-test methodologies, such as scan or built-in self-test. The methodology thus lets you increase ASIC fault coverage. Iddq testing looks for current leakage paths where they normally shouldn’t be. Examples include shorts in the gate oxide of a MOS transistor, bridging shorts in the chip’s metallization, and leaky pin junctions. These problems are often difficult or even impossible to detect during conventional chip testing, which looks for problems when transistor nodes are stuck at a logic high or low.

Iddalyzer places a “soft” ring onto your chip. This ring disables logic that normally draws static current and then selects as many as 20 test vectors for Iddq testing, either from the scan-test vector set or from a set of functional test vectors. Iddalyzer applies these vectors to the chip to selectively control internal node states while monitoring chip current. The presence of current during application of one or more of the vectors indicates an Iddq problem. By applying Iddq test during production testing of a chip, you reduce the possibility of passing a chip that has passed normal stuck-at testing but might fail during device burn-in or when placed in the final system. Additional NRE charges for adding Iddalyzer test methodology to your design start at $10,000. -- by Jim Lipman

LSI Logic, Milpitas, CA. (408) 433-8000.