Electronic Design Automation: December7, 1995

PC-board-layout translators for ECAD system. Translation software lets you import your pc-board layout into RSI’s Parametric Pro/Engineer ECAD system for 3-D evaluation and simulation of component placement and other mechanical constraints. The translators, which support both through-hole and surface-mount technologies, work with design systems from Cadence, Incases, Intergraph, Mentor, OrCAD, Pads, Pcad, Protel, Redac, Tango, and Zuken. A 32-bit DOS translator costs $2495; Sun and HP Unix versions cost $4995. Router Solutions Inc, Newport Beach, CA. (714) 721-1017.

RF/analog library enhances Windows simulator. An optional library for the Windows-based SystemView analog, digital, and mixed-mode system simulator lets you incorporate actual analog circuits and components into your RF design. The library includes models for fixed and variable amplifiers; op amps; double-balanced mixers; power-splitter and -combiner circuits; couplers; diodes; RC differentiators; RL, RC, LC, and PLL filters; and coupled resonator pairs. The RF/analog library costs $525; SystemView V1.8 costs $2450. Elanix Inc, Westlake Village, CA. (818) 597-1414.

Epilog interface permits board-level timing. An interface between Nextwave’s Epilog Verilog-HDL timing simulator and the Synopsys Logic Modeling Group’s SmartModel library and ModelSource and LM-family of hardware-modeling products addresses board-level timing problems that Verilog alone overlooks. The interface lets you perform timing verification in one simulation run, even on boards with complex ASICs and field-programmable gate arrays. Epilog and the interface for the SmartModel library cost $35,000; the hardware-modeler interface is $12,000. Nextwave Design Automation, San Jose, CA. (408) 467-4300.

Upgraded signal-integrity tool. The XTK crosstalk and signal-integrity program offers an array of programmable graphical and analysis selections. It lets you perform signal-integrity simulation of critical nets, full boards, or complete systems. It also lets you export resulting waveforms from multiple sources, including Spice, previous XTK simulations, and spreadsheets. The updated software also offers bus and time-step features that provide a speed increase of up to 10× for worst-case nets and designs. Base price is $21,000. Quad Design, Camarillo, CA. (805) 988-8250.

Flowchart editor permits Verilog and VHDL code creation. SpeedChart Version 3.3, a graphical hardware-description-language-capture tool, performs flowchart editing from Verilog and VHDL descriptions. In addition to creating and editing design descriptions, SpeedChart’s Flowchart Editor lets you graphically insert, add, delete, and modify behavioral constructs. It also supports hierarchical designs. Base price is $16,500. Speed Electronic Inc, Santa Clara, CA. (408) 980-0884.

High-density ASIC delivers 3 million gates. Processed in 0.3-µm drawn-gate-length CMOS, the TC220 system-level ASIC family squeezes 3 million raw gates, or 1.9 million usable gates, onto a 17.5×17.5-mm die. The TC220 core includes an R3900 embedded processor, 8/16-bit CISC embedded controllers, DRAM, and circuits for MPEG and asynchronous-transfer-mode functions. Three macrocell variations provide gate delays of 41, 49, and 69 psec. I/O options include LVDS, PCI, Gunning transceiver logic, and Rambus, as well as analog PLL. Prototypes will be available in the first quarter of 1996, with production quantities expected by the third quarter. Toshiba America Electronic Components Inc, Irvine, CA. (800) 879-4963.

IEEE VITAL 3.0 standard-compliant model generator. VitalGen generates VHDL Initiative toward ASIC Libraries (VITAL)-compliant ASIC and field-programmable gate-array (FPGA) libraries compatible with any VITAL-compliant simulation environment. To use the tool you describe an ASIC or FPGA model using one of the tool’s customized editors. The tool generates correct-by-construction VITAL-compliant source code and an accompanying test-bench shell. A single-user license costs $15,000. A Unix turnkey package is also available for $10,000 more. VHDL Technology Group, Bethlehem, PA. (610) 882-3130.

Cell-characterization tool and library generator for ASIC and logic design. Personal Toolbox, an addition to the company’s library-development tool family, is process-independent. It acquires cell information from Spice netlists and automatically creates simulation, synthesis, and timing models for the cells. The tool works in structured-custom and advanced-ASIC designs needing new cells. The tool runs on Sun, Hewlett-Packard, and IBM workstations. Prices start at $55,000 for a node-locked license. Meta-Software Inc, Campbell, CA. (408) 369-5400.

Tool speeds submicron interconnect analysis. PsiCrunch 2.0 accelerates interconnect analysis by compressing parasitic RC data for fast analysis of large, complex, IC designs. According to the company, the 2.0 version of the product compresses RC data by an average of 95 to 98%, speeding interconnect simulation two to 100 ×. The compression does not alter the accuracy of the circuit analysis. The tool runs on Digital Equipment Corp, Hewlett-Packard, IBM, Silicon Graphics, and Sun workstations. Prices start at $49,000. Integrated Silicon Systems Inc, Research Triangle Park, NC. (919) 941-6647.