Out in Front: December 21, 1995

Vendors continue to introduce ICs for disk-drive read/write channels, which provide performance beyond that of traditional peak-detection architectures (EDN, Sept 14, 1995, pg 24 and Oct 12, 1995, pg 30). Vendors are balancing these devices’ power consumption, performance, size, and cost in an attempt to solve the signal-processing challenge of recovering data bits from a noisy, varying channel at rates of approximately 200 Mbps. To address this challenge, vendors are employing new techniques using both analog and digital implementations of partial-response, maximum-likelihood (PRML) detection, as well as an adaptive-equalization technique developed for modems.

One of these devices, Motorola’s MC34250 IC, is a 200-Mbps PRML circuit that uses analog circuitry. It consumes 800 mW at 5V and comes in a 10×10-mm, 64-pin TQFP. The MC34250 comprises read- and write-channel functions, including AGC, filters, a transversal equalizer, a Viterbi detector, a frequency synthesizer, an embedded servo demodulator and pulse detector, an encoder/decoder, a data randomizer, and fault-tolerant synchronous detection.

Using an analog continuous-time tapped delay line in the transversal equalizer avoids the transport delays common to sampled data systems. These delays degrade phase margin and reduce format efficiency. In the MC34250, timing, gain, and data recovery subsystems sample the signal after read-signal equalization, which allows drive makers to use preambles less than 10 bytes long. Motorola fabricates the IC in 0.5-µm BiCMOS. You can selectively power down functions to minimize power consumption. The device costs $19 (10,000).

Philips Semiconductor takes a different tack in the read-channel market with the DF99XX family, also rated at 200 Mbps. Unlike PRML devices, these ICs use analog circuitry to implement decision-feedback-equalization (DFE) techniques, used in low-speed modems, to achieve user bit-density factors of 2.5 to 2.6, compared to approximately 2 for PRML and 1.4 to 1.5 for older peak-detection architectures. To minimize intersymbol interference, DFE has a forward equalizer that passes data through a summing junction to a decision block that produces output bits. DFE also feeds output bits back to a feedback-equalizer filter and sends that output to the summer for subtraction in a classic adaptive closed-loop approach.

The controller directs the IC to write to and read back from the disk known data, and the read channel adjusts its internal equalizer coefficients until it recognizes the correct data pattern. The device stores these "optimum" coefficents in RAM, and the adaptive process can occur during factory setup, drive power-up, or normal read/write operations. The RAM DFE and adaptive algorithm compensate for nonlinearities in the write process and read/write head.

The ICs in the 64- to 200-Mbps family also include standard read-channel functions of timing recovery, synchronization, write/idle clock synthesis, servo demodulation, and endec with various coding formats. Power consumption of the 200-Mbps BiCMOS member with all sections powered up is 750 mW; in sleep mode, the IC idles with 5 mW. The device is available in a 64-lead LQFP and costs $25 (5000). -- by Bill Schweber

Motorola Inc, Phoenix, AZ. (602) 413-5353.
Philips Semiconductors, Sunnyvale, CA. (408) 991-4022.