Electronic Design Automation: December 21, 1995

Verilog HDL tools gain FSM editor and synthesis translator. Veritools is adding Speed Electronic’s finite-state-machine (FSM) editor and synthesis translator to Veritools’ Verilog hardware-description-language (HDL) tools. Called Verichart, the integrated software lets you graphically capture state-machine descriptions and translate them into the Verilog register-transfer-level synthesis format. Verichart is available on Sun and Hewlett-Packard workstations for $10,000. Speed Electronic Inc, Santa Clara, CA. (408) 980-0884.

Programmable-logic tool runs under Windows 95. The Max+Plus II EDA tool now supports the 100,000-gate Flex 10K family of PLDs and operates with Windows 95. Version 6.0 also adds VHDL Initiative toward ASIC Libraries (Vital) model support and standard-delay-format back-annotation to its support for VHDL, Verilog, and Electronic Design Interoperability Format. With Max+Plus II, you can enter embedded blocks, such as RAM, ROM, multipliers, and FIFO buffers, in both schematics and hardware-description languages using a library of parameterized modules. Max+Plus II development tools are available for PCs, with prices starting at $495, and on HP, IBM, and Sun workstations. Prices for systems supporting the Flex 10K family start at <$2000. Altera Corp, San Jose, CA. (408) 894-7000.

Utility manages parts for OrCAD. The Design Data Link+ management system interfaces your parts database with the OrCAD design environment. Eliminating hand entry of part information into a schematic diagram, Design Data Link+ automatically transfers relevant information to the schematic, generates a bill of materials, and assists in part selection. It costs $250 and is available as part of OrCAD Capture for Windows and OrCAD SDT. Q Point Technology, Los Altos, CA. (415) 969-1649.

Software builds executable models of real-time systems. Statemate 6.0, a system-design-automation tool, lets you create executable models or virtual prototypes of embedded systems. The tool graphically models a system’s design to validate the system’s behavior and functionality. Version 6.0 offers expanded language and data-management capabilities, such as queues, records, unions, and user-defined data types, as well as an enhanced simulator. It is available for SunOS/Solaris, HP-UX, IBM AIX, and VAX/VMS platforms. Prices start at $25,000 for the first seat. i-Logix Inc, Andover, MA. (508) 682-2100.

Design software enhances support for FPGAs. The Galileo tool suite provides an integrated design environment for simulation, synthesis, and timing verification of field-programmable gate-array (FPGA), complex-PLD, and ASIC designs. Release 3.1 offers additional architectural support for AT&T Orca, such as global set/reset and the generation of preference files, as well as Electronic Design Interoperability Format (EDIF) support for the Orca FPGA foundry. V3.1 also provides EDIF flowcharts for Altera and Actel devices. Galileo V3.1 runs on Windows, Hewlett-Packard, and Sun platforms. European pricing starts at $12,000 (Windows) and $25,000 (HP and Sun). Exemplar Logic Inc, Alameda, CA. (510) 337-3700.

Windows-based program performs analog/digital simulations. Comprising a schematic editor and analysis engine, Micro-Cap V is a mixed-signal simulator for Windows 3.1, Windows NT, and Windows 95. It seamlessly integrates a PSpice- and Spice-compatible analog simulator with a native, event-driven PSpice-compatible digital simulator. The program performs analog and digital behavioral modeling, schematic waveform probing, Monte Carlo analysis, and parameter stepping. Micro-Cap V also comes with a library containing >7500 models. The software costs $3495. Spectrum Software, Sunnyvale, CA. (408) 738-4387.

Tool generates Vital '95 library models. A VHDL Initiative toward ASIC Libraries (Vital) ’95 (IEEE 1076.4-1995) model generator joins the Mercury line of library-development tools (LDTs). The LDT automatically generates and verifies sign-off-quality models for simulators that comply with the Vital '95 specification. Prices for the model generator start at $60,000/license; a license for current Mercury LDT users costs $30,000. Compass Design Automation, San Jose, CA. (408) 433-4880.

HDL tool performs gate/behavioral-level simulation. Continuum-QuickHDL, a mixed-signal simulation environment, combines analog and digital gate-level simulation with VHDL and Verilog behavioral-level simulation. A/D and D/A converter modules are written in VHDL, yielding simulations that are 20× faster than pure analog simulations. The reason: The VHDL model needs to compute the converter’s behavior only once per clock, rather than continuously. QuickHDL-VHDL, QuickHDL-Verilog, and QuickHDL Pro option licenses cost $15,500, $20,000, and $10,000, respectively, for current Continuum users. Mentor Graphics, Wilsonville, OR. (503) 685-8000.

Model simulates TMS-320C80 RISC DSP. A functional model of the TMS320C80 RISC DSP multimedia video processor is available for both the LM family and ModelSource 3000 series of hardware-modeling systems. Because the model uses the actual device in the simulation, it represents all device functions, including undocumented behavior. The C80 model, which costs $6000, requires two ModelSource 3000 systems and associated software. A variety of configuration options is available. Synopsys Inc, Mountain View, CA. (415) 962-5000.