Out in Front: January 4, 1996
Avantis, ArcCell-XO is a timing-driven layout system for cell-based chips using up to six layers of metal interconnect. ArcCell-XO represents the first product of Avanti, which ArcSys and Integrated Silicon Systems formed when they merged. Tightly integrated with synthesis tools from Synopsys, the tool lets you simultaneously choose the best timing, wire length, and wire congestion, reducing both chip size and total wire delay.
ArcCell-XO uses a proprietary timing-driven placement algorithm to consider all path timing constraints and routability for a chip. Instead of considering placement, global routing, and detailed routing as separate operations to be completed serially, ArcCell pipelines the operations to provide denser placement and faster routing convergence. After completing global routing, the tool does automatic 2-D compaction, preserving critical preroute patterns, such as clock-distribution networks and power and ground lines. ArcCell-XO also does clock-tree synthesis, including automatic buffer insertion and placement and balanced clock-line routing to minimize clock skew. You can also freeze blocks, so that ArcCell-XO cannot access them during compaction.
Preliminary benchmark results from ArcSys comparing ArcCell-XO to competitive routers show a 7 to 18% decrease in chip area for circuits ranging from 9000 to 75,000 cells. For the same circuits, ArcCell-XOs runtimes ranged from one to 17 hours on a SPARC5 workstation with 256 Mbytes of memory. You can get ArcCell-XO now as an option to ArcCell-BV, Avantis two- to three-layer routing system. Prices are $165,000 for ArcCell-XO alone and $320,000 with ArcCell-BV.
-- by Jim Lipman
Avanti Corp, Sunnyvale, CA. (408) 738-8881