EDN — 01.18.96 editorial

Editorial: January 18, 1996

Steven Leibson,
Editor In Chief

Design for test—or else. . .

Recently, I moderated an all-day design-for-test (DFT) seminar sponsored by Asset Intertech, National Semiconductor, and Synopsys. Odds are, you weren’t there. What follows are my opening remarks from the seminar, for your thoughtful consideration. If you have not looked at DFT methods in a while, this is a good time to do so. Design teams must use DFT methods, or they will quickly fall behind in today’s competitive markets.

"November 1995 marked the 10th anniversary of the development of boundary-scan standards. Back in 1985, Alcatel started the test-bus study group that became JTAG, or the Joint Test Action Group. Philips quickly took over the JTAG bandwagon and started driving it. JTAG hooked up with the IEEE’s P1149 serial-test-standard working group and the combined efforts eventually resulted in the 1149.1 standard.

"Surface-mount technology, with its fine component lead pitches and reduced pc-board geometries, has accelerated the problems of testability. Here’s what I wrote about testability in my Decade 90 series published seven years ago in EDN:

'Many design engineers’ and managers’ attitudes about product testability seem to have frozen during an earlier era in electronics, when a technician could troubleshoot almost any problem in 20 minutes with a scope and a little savvy. For products designed without the design-for-testability philosophy, today’s most advanced in-circuit ATE testers can do no more than automate the time-honored tradition of sticking a test probe into a failing test node to find the problem. But as electronic systems grow in complexity, this approach grows less and less effective and increasingly costly.’

"In an epoch of world-shattering upheavals in electronic technology, it’s amazing how slowly some things change. Here’s what EDN’s test-and-measurement editor Dan Strassberg wrote about boundary-scan testing in his cover story published in October 1993:

'As boards become increasingly dense, nodal-access problems of the kind once thought to be unique to multichip modules are affecting more and more boards. Boundary-scan testing is about the only game in town for overcoming these problems. But, like nearly every new technology, its acceptance has been hindered by a poorly developed infrastructure and, possibly, by a bit too much early optimism from partisans.’

"Our mission today is to convince you that much of that missing infrastructure is now developed, in the form of silicon, EDA tools, and test systems. You can and you should now be designing your products for testing."

Steven H. Leibson
Editor in Chief