EDN — 01.18.96 EDA tool for 3-D-design optimization

Out in Front: January 18, 1996

EDA tool for 3-D-design optimization

Epic’s AMPS (Automatic Minimization of Power through Sizing) tool lets you optimize ASIC chips for speed, power, and transistor area. The tool makes transistors in a circuit larger or smaller to meet your design criteria and maintain circuit functionality. You use AMPS before chip layout, with estimated capacitances, to meet design targets and after layout, with back-annotated parasitic capacitances, for final optimization and verification.

When performing an optimization, AMPS runs three analyses to find the starting point providing the best results: leaving all transistors at their initial sizes, scaling all transistor widths by a common factor, and making all transistors the same width. By picking the best starting point, the tool reduces the time to find the best solution. You then specify the type of design optimization you want for your design: meeting a delay goal and minimizing power and area; meeting a power goal and minimizing delay and area; making all timing slacks positive and minimizing power and area; or specifying the relative priorities of power, speed, and area, either as an ordered list or with weighting factors, and having AMPS attempt to meet all criteria.

Although AMPS works automatically, you can control many parameters before and during optimization. If you need to maintain critical transistor ratios in sections of a design, you can preserve these ratios during resizing. You can also specify "don’t-touch" areas of the design, blocking AMPS from resizing devices in analog or critical digital areas. You can also tell AMPS the maximum number of iterations to use for an optimization. After each iteration, AMPS saves and reports the results and allows you to change the optimization criteria. The report also includes a list of all saved transistors and their new sizes.

Your input to AMPS is a standard netlist in Spice, Verilog, or EDIF (Electronic Design Interchange Format). Epic is also developing a VHDL version. You also must supply power-simulation vectors and a technology file that includes some process parameters. During its optimization, AMPS takes into account nodal activity, fan-in, and fan-out. You can use AMPS for designs ranging from 100 to 30,000 transistors, including ASIC chips and library-cell development. AMPS is available now on Hewlett-Packard, IBM RS/6000, and Sun SPARC workstations. Prices start at $90,000. — by Jim Lipman

Epic Design Technology,
Sunnyvale, CA. (408) 988-2997.