Out in Front: January 18, 1996
The key tool is Watt Watcher/Architect, because you can use it before you do any circuit synthesis. Watt Watcher/Architect is hierarchical; you use it on complete chip designs. It offers fast execution time, allowing you to perform various "what-if" analyses on a design to determine which of several architectural configurations meet your power budget. Typically, you supply a Verilog description and a stimulation vector file to the tool. Watt Watcher/Architect uses synthesis technology to infer the circuitry of the design and to analyze its power requirements. Watt Watcher/Architect uses "state-dependent" memory power modeling to accurately estimate memory blocks. The tool also estimates design size and clock loading, providing a reasonable estimate of the power that the clock circuitry consumes. After an analysis, Watt Watcher/Architect gives you the designs total dynamic and static power consumption, the power each module consumes, the power the clock circuits consume, net activity, and other design-critical information. You then review the results, in a graphical format, to determine which portions of the design you may need to change to reduce power. Watt Watcher/Architect costs less than $40,000. Watt Watcher/Gate costs $5000. Both are available on Sun and Hewlett-Packard workstations. by Jim Lipman
Sente Inc,
Chelmsford, MA. (508) 244-1100.