EDN — 01.18.96 electronic design automation

Electronic Design Automation: January 18, 1996

Technology-independent ASIC library is Vital-compliant. The vendor’s ASIC library offers full Vital support and covers technologies ranging from 1.0-, 0.8-, and 0.6-ľm gate arrays through 1.0-, 0.8-, and 0.6-ľm standard cells. The company accepts structural VHDL netlists and provides SDF back-annotation files produced from a proprietary delay calculator that gives Vital models Spice-like timing accuracy. There is no charge for the library’s use. American Microsystems Inc, Pocatello, ID. (208) 233-4690.

Testability analyzer cuts debug time. DFTInsight, a graphical-testability-analysis tool, reduces test-debugging time for fault analysis and design rule checking by up to 50%. The program generates schematic fragments to isolate design-for-testability errors, and filters out irrelevant gates and components. Only the portion of the design that is contributing to the problem is displayed, even if it resides across multiple levels of hierarchy. DFTInsight, which runs on HP-PA, IBM RS6000, DEC Alpha, and Sun SPARC workstations, costs $25,000. Mentor Graphics, Wilsonville, OR. (503) 685-7000.

Windows program spots pc-board transmission-line problems. BoardSim V1.45 signal-integrity software checks design rules on an entire pc board. It runs under Windows 95 and includes a tool bar for commonly used commands. The program includes enhanced algorithms for analyzing complex net topologies and flags warnings for unterminated nets that are too long. V1.45 accepts data from a broad range of pc-board-layout packages, including those from Accel, Cadence, Mentor, and OrCAD. Prices range from $1895 to $3495, depending on the pc-board-layout package. HyperLynx Inc, Redmond, WA. (206) 869-2320.

Verification software supports RTL and transistor designs. Design Verifyer 2, a second-generation verification program, adds full support for synthesizable Verilog RTL, an extended-data representation for transistor-level circuits, and algorithm enhancements to verify complex arithmetic circuits. Because Design Verifyer 2 uses a mathematical proof, the verification is complete and requires no simulation vectors. The formal verification software runs on SPARCstation, HP 9000/700, and IBM RS/6000 platforms. A single-user floating license costs $95,000. Chrysalis Symbolic Design Inc, Billerica, MA. (508) 436-9909.

VHDL generators read Xilinx netlists. Additions to the VBAK family of VHDL generators embrace Xilinx FPGAs, including the XC2000, XC3000, XC4000, and XC5000 LCA series. Using Xilinx Netlist Format (XNF) files, VBAK/VITAL produces a gate-level netlist suitable for pre- and post-layout timing verification using Model Technology’s V-System or Mentor Graphics’ QuickVHDL simulator. VBAK/SST produces an RTL file for fast functional simulation and synthesis using any IEEE 1076 standard tools. VBAK/VITAL and VBAK/SST carry the same price: $1995 for Windows PCs and $4995 for Unix workstations. Topdown Design Solutions Inc, Nashua, NH. (603) 888-8811.

Generation software permits library reuse. ICGen, a process-portable module-generation program for deep submicron library design, reduces development time and costs by letting you reuse designs. ICGen lets you build dense library cells, capture key design elements, and automatically rebuild the cells to incorporate new process technology and other design-rule changes. The software runs on SPARC and HP-PA platforms under Sun OS and HP-UX, respectively. A stand-alone license costs $55,000; floating licenses cost $68,750. Mentor Graphics, Wilsonville, OR. (503) 685-7000.

Mixed-signal simulator runs under Windows 95, NT. Electronics Workbench V4.1 offers a Spice simulator that is three times faster than V4.0 and is compatible with Windows 95 and NT. Schematic files created with the mixed-signal simulation tool can be exported to pc-board design packages, including OrCAD and Tango, using pc-board export. A Spice I/O feature lets you import and export files to other Spice-based simulators. Version 4.1 costs $299. With pc-board export, Spice I/O, and more than 2000 additional models, the device costs $599. Interactive Image Technologies Ltd, Toronto, ON, Canada. (416) 977-5550.

VHDL models simulate Pentium- and Pro-CPUs. Bus-functional compiled simulation models for Pentium- and Pentium-Pro processors are available for a variety of VHDL simulators, including Cadence Leapfrog, Mentor QuickVHDL, and Viewlogic ViewSim. The models, which use Intel-verified source code and include VHDL Testbench and Bus Functional Language files, run on Windows and Unix platforms. Models cost $5000 each. An introductory pricing program provides a 50% model-price discount for orders placed by the end of January. Computer Aided Software Technologies Inc, Pomona, NY. (914) 354-4945.