Tom Botker 
Design Feature: February 1, 1996
Tom Botker
The INA116 ultralow input-bias-current instrumentation amplifier design is the result of Tom Botker's work. His responsibilities included both the design and test of the IC, which breaks ground in performance, minimization of error sources, and stability over temperature ranging to 125°C. Botker also designed a 3-fA/sub-pF probe using the device.
Botker holds a BSEE from Iowa State University (Ames, IA) and is working on his MSEE from the National Technological University. He has published articles in magazines such as EDN and has a patent pending (with coworkers) for his work on the low-input bias circuit of the INA116.
Burr-Brown Corp, Tucson, AZ. (520) 746-1111
Hans Klein, PhD
Dr Klein's research in the field of analog CMOS led to the development of IMP's EPAC product family. Each EPAC contains a number of high-level analog cells or modules (such as amplifiers, comparators, filters, DACs, and multiplexers) that you can configure to provide the overall signal-processing functions needed.
Klein received his MSEE and PhD from the Technical University of Aachen (Germany), where his thesis and dissertation focused on CMOS mixed-signal and analog circuit design. He joined IMP in 1988 as director of design technology; he previously worked at the Institute for Microelectronics in Stuttgart, Germany. In addition to his EPAC papers, he wrote a paper on CMOS preamps for MR heads at ISSCC (1994), an invited paper at the Japan Solid State Conference (1994), and published a book on mixed-signal simulation. He also holds several other patents, in addition to those for his work on the EPAC device.
IMP Inc, San Jose, CA. (408) 432-9100
Kelly Beavers
Kelly Beavers, a founder and Executive Vice President of Engineering at Datasonix Corp, took a minuscule audio tape cartridge from Sony and adapted it to data-storage applications. The result is the tiny Pereos tape-backup system, a battery-powered device that stores up to 1.2 Gbytes of data in a cartridge that's about the size of a stack of postage stamps.
Adapting technology is not new to Beavers. At Exabyte, which he helped found in 1985, he participated in the adaptation of the 8-mm video cartridge to computer use. Before that, he gained 11 years of data-storage experience at Storage Technology. He earned his BSEE degree from the University of Denver in 1974.
The Pereos tape-backup unit uses helical-scan technology like that in VCRs and high-end tape systems, yet the unit weighs only 10 oz and runs on two AA batteries. Limited to only one motor, the unit has no servo for tracking, but the heads in a rotating drum pass over a data track as many as four times, providing multiple (and sufficient) opportunities for accessing data even without tracking. Two read heads and two write heads allow automatic read-after-write data verification.
The combination of drive and tape technology used in Pereos allows data transfers at rates as high as 10 Mbytes per minute. A specially developed ASIC controls the unit; off-the-shelf controllers were either too slow or too expensive.
Datasonix Corp, Boulder, CO. (303) 545-9500
Ian Poynton & Ron Lorenz
Ian Poynton, a senior design engineer at Power Convertibles Corp, and Ron Lorenz, a member of the technical staff at California Power Research Inc, jointly developed the VKP60xT dc/dc converter, which is marketed by Power Convertibles. The VKP60xT is usable with one, two, or three outputs, with full-rated power in any combination. The device is the only half-pack, triple-output dc/dc converter with an output in excess of 40W. The inductor is coupled to all outputs in the VKP60xT, operating in the two quadrant loads and providing continuous current during all line and load conditions. The absence of overlapping conduction in the output Schottky rectifiers reduces rectifier and other conductor losses in the secondary circuit.
When Poynton and Lorenz developed the VKP60xT, there were no available loop-analysis tools for a full-wave buck/boost converter with a single inductor. Yet, such tools were essential for a short product-development cycle. Consequently, in not quite 10 months, the two engineers concurrently created their own design and analysis tools and developed and brought to market the VKP60xT. The set of design and analysis tools they developed allowed rigorous evaluation of applications for the product, including cost/performance properties. Patents on the tool set are pending.
Ian Poynton earned a BSEE degree from Leeds University in Leeds, UK. Ron Lorenz earned his BSEE at Michigan State University in East Lansing, MI.
Power Convertibles Corp, Tucson, AZ. (520) 628-8292
California Power Research Inc, San Diego, CA. (619) 530-1515
Wolfgang Schenke
Calling on his experience with the Peter Jordan Co in Offenbach, Germany and as one of the founders of Calay Systems, Wolfgang Schenke spent six years creating and bringing to market a line of software products that allows pc-board design engineers to cross-utilize a broad range of CAD systems. With products from Schenke's company, Router Solutions, board designers can translate all the information needed between two CAD environments, including libraries, placement, netlists, traces, text, and copper area. Router Solution translators are available for DOS, Unix and Windows systems. Using Schenke's software innovations, designers can consolidate pc-board CAD with fabrication and testing across different design platforms and vendors, giving the engineer a broad degree of design flexibility. Schenke has also developed graphics translators to integrate mechanical systems into pc-board CAD systems. Using these tools simplifies documenting and publishing pc-board designs in common CAD systems, including those from AUTOCAD, CADKEY and Intergraph.
Router Solutions' flagship product, CAMCAD for Windows, is an interactive, multipurpose translator tool for 2D graphics files that uses Schenke's innovative developments for pc-board design. Combining various software modules, designers can read from and write to a broad range of CAD formats. CAMCAD even allows designers to create and view a complex drawing composed of multiple drawings using different data formats, units, and scale factors. Designers can export CAMCAD's graphics output to many popular pc-board design systems, including those from PADS Software, PCAD, Protel, Accel, Redac, OrCAD, and Mentor Graphics.
Router Solutions Inc, Newport Beach, CA. (714) 721-1017
TestMaster graphical tool
Teradyne, best known for hardware test, is tackling software. TestMaster, the first product from a software-test division, aims to solve one of the most pernicious and intractable problems in product development: bug-ridden software and firmware. By simplifying the design of structured and rigorous software-test protocols, TestMaster controls development and quality-assurance costs and makes development schedules more predictable. The workstation-based package costs $50,000 for a floating license.
Instead of following a vague plan to search for bugs, TestMaster uses a systematic approach based on a patented Model Reference Technology. Test generation depends not on the actual code but on a functional specification that models the behavior of the software you are testing. This specification is not a verbose, inscrutable document. Rather, it is a graphical depiction of the software operation. Developers can interact with the model at the workstation console. Because of the model-based approach, design of test protocols can begin even before code is available to test. Early in the development process, the model indicates how the software will operate.
The tool lets developers determine how many tests must run to examine every possible situation. Developers who choose to test less thoroughly can obtain estimates of the likelihood that bugs will remain. As developers modify segments of code, they can test only the affected areas. The tool automatically generates the code that runs the tests. Teradyne Inc, Software and Systems Test. Nashua, NH. (800) 996-8778
THS 720 Tekscope
Tektronix's $2195 8.5×7×2-in., 3-lb THS 720 TekScope brings the performance of benchtop instruments to handheld DSOs that include DMMs and LCDs. The unit has two 100-MHz-bandwidth channels, each with a dedicated ADC that samples in real time at 500M samples/sec. Moreover, the TekScope adds features, such as battery power and 600V-peak signal isolation, that don't exist in benchtop scopes. The $1795 THS 710 is similar to the THS 720 but offers 60-MHz bandwidth and 250M-sample/sec capture.
If you've looked at many LCD scopes, the TekScope's 4.7-in. (diagonal) 320×240-pixel display can stop you in your tracks. It isn't a color LCD. However, no monochrome LCD on a digital storage oscilloscope (DSO) matches this display's 10-fL brightness. The high contrast does exact a penalty in battery life, though. To make the 1¾-hr life between charges acceptable, Tek lets you charge the replaceable NiCd cells within the scope while the scope operates from an external ac adapter/trickle charger that doesn't defeat the signal isolation. You can also recharge the batteries outside the unit with an optional fast charger.
Each DSO input is isolated from the other and from the 4000-count DMM, from the RS-232C output, and from the chassis. On competitive isolated handheld DMM/DSOs, all inputs share a signal-common bus. Also, competitive 100-MHz-bandwidth units' scope channels share an ADC that doesn't sample fast enough to capture full-bandwidth, single-shot events. Other features of the THS series are a waveform memory of 2.5k samples/channel, 21 automatic measurement modes, the ability to store 10 waveforms and 10 measurement setups, and a user interface styled after that on Tek's TDS family of benchtop DSOs.
Tektronix Inc, Tools Business Unit. Beaverton, OR. (800) 426-2200
PCMCIA-1149.1 card
With the aid of the IEEE-1149.1 boundary-scan test standard and PC Card (PCMCIA) miniaturization technology, Corelis's PCMCIA-1149.1 turns notebook PCs into pc-board test systems. Such testers occupy approximately 1/1000 of the volume of conventional board-test systems and cost about 1% of the price.
Although production-test departments can use the tiny tester, the product's greatest beneficiaries are likely to be field-service, maintenance, and product-support personnel. Moreover, because the IEEE-1149.1 Test-Access Port (TAP) is rapidly becoming the industry standard for accessing the built-in self-test (BIST) features of devices, boards, and systems, the need for lightweight, portable, IEEE-1149.1 testers will only grow.
Corelis recognized the importance of low ownership cost in a product whose purpose is to make other products inexpensively maintainable. A company might use Corelis's VXIbus-based IEEE-1149.1 systems to test products before shipment and then use the PC Card tester for field support. Because the PC Card unit is compatible with the VXIbus-based systems, test programs developed for the factory work without modification in the field. The same development tools that Corelis customers use to develop test programs that run on the VXIbus-based testers are usable for developing programs that run on the PC Card unit.
The tiny tester is a two-channel device that handles vectors up to 232 bits long and clock rates up to 25 MHz. A special twisted-pair cable with extra ground leads couples the tester to the unit under test with a minimum of crosstalk. Corelis began shipping the $2450 unit in July 1995.
Corelis Inc, Cerritos, CA. (310) 926-6727
Quantox wafer monitor
Keithley Instruments' Quantox system measures parameters critical to assessing the quality of IC wafers, and does so without contacting the wafer under test. A vibrating Kelvin probe acts as a nonintrusive voltmeter that capacitively senses the wafer's surface potential. The system, which offers an alternative to MOS capacitance-voltage testing, measures the effective thickness of oxide layers and detects plasma-induced wafer damage. Because many of today's small-geometry IC processes use oxide layers thinner than 10 nm, oxide-quality measurements are becoming increasingly important in wafer processing. The noncontact technology allows the reuse of monitoring wafers, eliminating the costs and time delays associated with forming contacts on the wafers. Forming contacts can also change the measured parameters. The cost savings in one year in a facility that processes 8-in. wafers can easily exceed the Quantox system's ~$500,000 cost.
The system produces the effect of dc bias by using a corona source to deposit carefully controlled charges on the wafer under test. The principles that underlie the corona source are the same as those that underlie the corona sources in photocopiers. The Kelvin probe, which is connected to a null-detecting current meter, determines the potential gradient in and above the wafer by measuring the bias level that results from the corona source and the resultant surface-photo-voltage effects.
Finally, in contrast with other semiconductor process-monitoring systems, Quantox reduces the raw data into results that process engineers can quickly associate with process parameters. The system even flags results that vary significantly from the expected values.
Keithley Instruments Inc, Process Monitoring Group. Cleveland, OH. (216) 248-0400
Ultimod S switching power supplies
The Ultimod S series of modular switching power supplies is factory-configurable (with a five-day turnaround) for a broad range of applications. The family uses standard modules, including high-density Vicor (Andover, MA) dc/dc converters, to provide the required dc output voltages and power levels. The supplies provide as many as nine outputs, with total power levels as high as 1200W. The Vicor converter modules operate singly for 100 or 200W power requirements or in parallel for power levels to 1200W. The Ultimod uses an inventory of dc/dc converters with output voltages from 2 to 48V. You can configure the series for more than 3 million output configurations. The family comes in two case sizes: 5×5×11 in. with two output slots and 5×6.5×11 in. with three output slots.
Features include a power-factor-corrected (PFC) input and a large number of control-and-monitoring functions for interfacing with the host system. PFC results in a near-sinusoidal input current and low harmonic currents, as opposed to the high-amplitude current pulses inherent in noncorrected supplies. The internal output converters operate from a 385V-dc power bus produced by the PFC ac-input module. The converters use a variable-frequency (up to 2 MHz), zero-current switching topology. Because the supplies use standard, approved modules, safety-agency certifications are inherent in the units. The units have a ball-bearing, dc-powered fan. You can replace the fan in the field by removing two screws and unplugging it. The full-featured 1200W Ultimod costs $1475 for a single-output model and $1675 for a quad-output supply (1-9).
Unipower Corp, Coral Springs, FL. (954) 346-2442
VKP60xT series DC/DC converters
Available in eight models, the VKP60xT series of dc/dc converters provides a choice of two input ranges: 18 to 40V dc or 33 to 75V dc. Four selections of output-voltage combinations are available: 3.3 and ±12V, 3.3 and ±15V, 5 and ±12V, and 5 and ±15V. You can use the fixed-frequency, PWM converter as a single-, dual-, or triple-output converter, to provide 60W output power in all three configurations. The supply maintains full isolation for the three configurations, without cross-regulation degradation or the need to provide minimum loads. A sync-in terminal allows synchronization to an external clock or to the sync-out signal of a single-output VKP60xS module. The units operate with base plate temperatures from -55 to +100°C. Typical efficiency is 89% at full load. Each output has independent current limiting and 200V-dc floating-point isolation from other outputs.
Features include adjustable output voltages, remote enable, primary and secondary on/off pins, and 50-µsec transient recovery for a 0 to 90% load step. You can operate the units in two standby modes with the primary and secondary on/off pins. The primary control allows the supply to dissipate lower internal power than that obtained with the secondary control. All outputs have independent current limiting. The primary channel enters current limiting at approximately 75W total-supply output power; the auxiliary channels start to limit at approximately 40 to 45W total-channel output. Under a short-circuit condition, the output current is typically 80 to 100% of the rated nominal value. The supplies conform to safety standards UL1950, EN60950, and CSA 22.2 #234. $113 (100).
Power Convertibles Corp, Tucson, AZ. (520) 628-8292
AA32A series voltage-regulator modules
The AA32A series of voltage-regulator modules meets the high di/dt requirements of Pentium Pro microprocessors. The devices limit output-voltage deviation to within 5% of nominal voltage and supply Pentium-load transients of 9.5A in 350 nsec. These transients correspond to a load slew rate of 27A/µsec. The input structure of the AA32A concurrently limits the input-current slew to less than 0.1A/µsec to prevent the input source from dropping out of regulation. To satisfy these current-slew demands, the regulators rely not only on high-gain amplifier circuitry, but also on low-ESR, input-and-output capacitances that supply the current during the initial few microseconds, before the input source reacts and supplies the additional current required.
The AA32A derives its input power from either the 12V rail (Model AA32A-012L-035S) or from the 12 and 5V rails (Model AA32A-005L-035S) to generate the 2.9V that the Pentium Pro typically requires. To support the voltages that future members of the Pentium family will require, the AA32A offers four voltage-control inputs that accept a 4-bit code. The code selects one of 15 output voltages, ranging from 2.1 to 3.5V. Features include an output-enable pin and a power-good function that indicates when the output error exceeds ±7% of the set voltage. The ±5% output-regulation specification includes the cited 9.5A load transient, ripple and noise, thermal drift over 0 to 60°C, and load-and-line regulation. The supplies come in a 3.1×1.5×1-in. case and meet UL flammability specs per 94V-0. The units come with either a 40-pin interface socket ($30 (1000)) or F pins ($27.46 (1000)).
Astec America Inc, Carlsbad, CA. (619) 757-1880
PowerShield ISDN series uninterruptible power supplies
The PowerShield ISDN 10W series of uninterruptible power supplies (UPSs) provides battery-backup power for ISDN customer premises equipment (CPE) and the NT-1 interface. Replacing the ac adapter provided with the ISDN NT-1 unit, the UPS provides a nominal -48V of backup power to the S/T or U interfaces of ISDN equipment. The PowerShield provides one hour of backup time with the maximum 10W load and five hours with a 2W load. Adding the optional XBP extended battery pack triples these run times. The UPS provides reverse-polarity PS/2 power during a utility-line failure, thereby triggering the energy-saving sleep mode most NT-1s and CPE support. The PowerShield also protects ISDN equipment from power surges and spikes on the ac line.
The rationale for a battery-backup system for ISDN installations is that ISDN, unlike normal telephone service, requires separate power from the utility line. Features include audible and visual indicators on the PowerShield that allow you to monitor changes in power conditions and automatic self-test of the battery. The visual indicators comprise a red and green light. In normal on-line operation, the green light is on continuously. In the absence of line power, a flashing green light and a beeper warn you that the system is operating on battery-backup power. When the battery in the UPS is low, the red light is on continuously, and the beeper sounds. If the UPS detects a weak battery, the red light flashes, and the beeper sounds. You can install the UPS either at the CPE or near the NT-1 interface. Prices are $149 for the PowerShield ISDN and $99 for the XBP extended-battery pack.
American Power Conversion, West Kingston, RI. (401) 789-5735
MBGA Packages
The MBGA package for ball-grid-array (BGA) chips has an anodized-aluminum substrate. The anodic layer forms the dielectric layer between the aluminum and a thin-film circuit layer. A sputtered-and-plated, copper-nickel-and-gold thin-film layer is directly deposited on the anodized aluminum. An epoxy solder-mask material covers the thin-film layer. The assembly operation comprises die-attaching the chip into a cavity in the aluminum substrate, wire-bonding to the traces on the substrate, encapsulating with a liquid encapsulant, and solder-ball attaching. Thermal resistance of the MBGA system is low, because the substrate is in direct contact with the chip and circuit layers, thereby acting as a heat sink.
The substrate also acts as a floating ground plane and reduces lead inductance and mutual capacitance. You can connect the substrate as an active ground plane to further reduce noise and parasitics. The inorganic substrate in the MBGA eliminates the moisture-transmission path inherent in plastic BGAs. The package with 17-mm chips has undergone 1000 temperature cycles with no chip cracking or loss of stud-pull strength. Thin-film adhesion strength is greater than 1200 psi, with no indication of blistering or peeling after 1 hour of 390°C heat stress. Additionally, the MBGA offers a minimum breakdown voltage of 500V between the thin-film and aluminum substrate. A mounted height as low as 1 mm is achievable. Price is a function of chip size and pinout count.
Olin Interconnect Technologies, Manteca, CA. (209) 824-6506
Z4D-A01 sensor
The Z4D-A01 optical-displacement sensor has reflective technology that uses the theory of reflective triangles to detect extremely small movement and thickness of objects. The device incorporates a position-sensing-diode (PSD)/LED combination that provides information about the total displacement of an object. For example, the Z4D-A01 can resolve 10-µm movement and paper thickness at a sensing distance of 5.5 to 7.5 mm. The PSD chip receives reflected IR light and supplies a two-signal analog output. This output is a function of the position at which light reflects on the PSD chip, rather than a function of the quantity of light received. Light falling on the PSD chip changes position in proportion to the object's movement. Thus, neither an object's color nor its angle relative to the sensor has a significant effect on the sensor's analog output. Sensing distance is 6.5±1 mm for detecting white paper with a 90% reflection factor. A constant-current source drives the IR LED, rendering it immune to current surges caused by supply-voltage fluctuations. The 10-µm distance resolution allows the Z4D-A01 to sense the thickness of a single sheet of paper and to detect either the number of sheets of paper in a feeder or the position of a sheet of paper as it travels through the paper path. The sensor comes in a package that measures 25×23.5×20 mm. Price is $45 in single-unit quantity.
Omron Electronics Inc, Schaumburg, IL. (707) 843-7900
Silver in Glass family of encoder elements
The Silver in Glass family of encoder elements uses thick-film technology to provide a long operating life in harsh environments. The encoders, combined with one or more moving contacts, offer a switching function to measure position or speed. The technology consists of a smooth glass layer placed on a ceramic substrate. A conductor layer, printed on the glass layer, uses a low-temperature glass phase that melts and partially diffuses the conductor into the glass layer. The process yields a smooth conductor that exhibits long life and little contact wear. Custom versions of Silver in Glass encoders can incorporate resistors, potentiometer elements, and analog signal-conditioning circuitry.
Competing encoders use optical, metal-foil, and printed-circuit technology. Optical encoders are appropriate in applications requiring millions of cycles; however, high temperatures, vibration, and contaminated environments can cause reliability problems. With metal-foil and printed-circuit encoders, rotational-life and electrical-noise problems limit applicability. Silver in Glass encoders provide rotational life to 20 million cycles and offer high immunity to high temperatures and vibration levels. The DE-2 series of encoders uses the Silver in Glass technology on one side of the element and a hybrid circuit for signal conditioning on the other side. These (primarily) custom products range from $4 to $25, depending on the design and production volume.
Spectrol Electronics Corp, Ontario, CA. (909) 923-3313
FPF42C10660UA plasma display
The FPF42C10660UA full-color plasma display provides 42-in.-diagonal viewing. The device is the largest direct-view flat-panel display to offer a viable alternative to a CRT, at one-tenth the depth and one-sixth the weight of a picture tube. The display provides 16.7 million colors, 300-cd/m2 luminance, 160° viewing angle, 70:1 contrast ratio, and 852×480-pixel resolution in a 16:9 aspect ratio. Its package measures less than 3 in. thick and weighs less than 40 lbs.
The structure of the panel uses a pair of parallel, transparent-display electrodes on the front glass panel. A discharge cell behind the front panel contains a neon-xenon gas mixture. An MgO layer on the rear of the front panel produces a surface discharge when a voltage energizes the front-panel electrodes. The layer generates UV rays. The UV rays excite phosphor dots on the rear glass plate, emitting visible light through the front plate. The FPF42C10660UA requires three external power supplies: 160 to 190V at 1.7A, 40 to 70V at 2A, and 4.75 to 5.25V at 5A. The price of the panel is $10,000 for engineering samples; in volume production later this year, the price will be $5000 per panel.
Fujitsu Microelectronics Inc, San Jose, CA. (408) 922-9000
RSC-164 speech-recognition IC
The RSC-164 is a low-cost, speech-recognition IC for consumer electronics. The device combines an 8-bit µP with neural-network algorithms for speaker-independent and -dependent speech recognition. The chip allows speech synthesis, voice recording and playback, four-voice polyphonic music synthesis, and speaker verification. The chip boasts >96% recognition accuracy. The CMOS device contains 384 bytes of RAM, 64 kbytes of ROM, a 12-bit ADC, a 10-bit DAC, and 14 general-purpose I/O lines.
The RSC-164 uses a pretrained neural network to perform speaker-independent speech recognition. The device achieves speech synthesis using a time-domain compression algorithm that improves on conventional adaptive-differential pulse-code-modulation algorithms. Dynamic AGC control compensates for users not positioned optimally near the microphone and for people speaking too softly or too loudly.
The device uses silicon design and neural-network algorithms. The silicon design uses 0.6-µm technology and combines the core processor with A/D and D/A circuits. The neural-network speech-recognition IC preprocesses the raw acoustic signal into a rate and distortion-independent representation that is fed into the neural network. The net can perform a nonlinear Bayesian neural classification.
The network contains an explicit probabilistic model. Prior class probabilities can be incorporated, and the network outputs can be interpreted as a probability distribution over classes. The training procedure explores the space of neural-network models as well as weighting coefficients; cross-validation techniques are used for model selection. Training data consist of 300 to 600 voice samples representative of potential users. The RSC-164 has applications in consumer-telecommunications devices, security products, personal digital assistants, wireless devices, smart home appliances, and toys and books. The chip costs $3.75 for 100,000 units/year.
Sensory Circuits Inc, San Jose, CA. (408) 452-1000
AHA3410 StarLite coprocessor
The AHA3410 StarLite coprocessor is a single-chip CMOS device that implements a lossless compression and decompression algorithm. The algorithm exhibits a compression ratio of greater than 4:1 for bit-mapped image data. The chip compresses and decompresses rasterized bit-mapped image data in hard-copy systems, such as printers, copiers, scanners, and plotters. The chip lets these systems compress an entire page in the background when another page is printing.
The chip compresses and decompresses data at a rate of 25 Mbytes/sec. The chip also handles a 100-Mbyte/sec burst-data rate over a 32-bit data bus. The speed enables the chip to process more than 90 pages/min at 1200-dpi resolution on standard 8.5311-in. documents. The chip also provides a glueless interface to AMD's 28K, Intel's 960, and Motorola's 68K embedded processors.
The chip compresses data by transferring 32-bit words through its 32-bit data port into the compressor-input FIFO buffer in single word or burst transfers. Optionally the data may come from an 8-bit video-input port. This flexibility permits in-line or look-aside architectures. The chip outputs the compressed data in single word or burst transfer through the 32-bit data port, which can transfer 100 Mbytes/sec.
The chip decompresses a compressed data stream by transferring the data through the 32-bit data port and into the decompression input FIFO buffer. The decompression module then decompresses the data and outputs the data either out the video port or the 32-bit data port. The chip's innovative capabilities include the algorithm, simultaneous compression and decompression feature, and high-speed bus throughput. The chip costs $54.76 for the first 5000 units and $36.70 for the next 5000 units.
Advanced Hardware Architectures, Pullman, WA. (509) 334-1000
Plexicoder keyboard encoder
The Plexicoder series of keyboard encoder ICs meets the requirements specific to the handheld and portable computing market. These requirements include low-power and minimal use of real estate. The devices draw 2 µA of current when active and 2 mA when inactive at 5V. (The device also operates at 3.3V.) The Plexicoder comes in a 44-pin quad-flat package. Features are built into this small package. For example, the series provides features such as sticky keys, "any key wake-up," two-tone audio output, Windows-key support, and an external peripheral-connection port for PS/2 devices.
The Plexicoder offers overall system power-management features. Acting as the sole power-on device, the Plexicoder can actively control leakage currents to unpowered peripherals. The devices provide a direct interface for digital EEPROM potentiometers typically used for LCD contrast, brightness, and audio-volume control in portables. This feature simplifies design and eliminates the need for buttons or knobs external to the keyboard. The encoder controls the settings of these devices either through keyboard input or through commands from the system. The encoder memorizes the settings of the controlled devices in its internal memory. The device can increment or decrement settings with programmable steps.
The series uses the company's self-power management method to attain zero-power performance. This method enables the encoder to power-down during periods of inactivity, including the time in between keystrokes. For system power management, you have the option to power down attached peripherals as well. Such peripherals include LEDs, external keyboards and mice, and the 8042 keyboard controller. In addition, the Plexicoder can detect the powered-down condition of these devices and can actively control leakage currents to the unpowered devices. One version of the series also supports the System Management Bus, the control bus for smart batteries. Using this version you can get the present state and calculated battery information and command a recharge through a software interface. $2.29 (OEM).
Usar Systems, New York, NY. (212) 226-2042
BtV MediaStream chip set
The BtV MediaStream multimedia-accelerator chip set combines 2- and 3-D graphics and video-acceleration, audio-control, and DSP functions in a unified architecture. The hardware is fully integrated with a support library of utilities, drivers, and BIOS to allow OEMs to bring multimedia to the market. The chip set includes the BtV2115/2125 2- and 3-D accelerator chips, the BtV2210 digital game port and MIDI controller, the BtV2488 packetized data DAC (PACDAC), the BtV2300 AudioStream interface, and the BTV2811A VideoStream decoder.
The BtV MediaStream chip set combines audio and both 2- and 3-D video and graphics so that multimedia PCs no longer require multiple boards and chip sets from often conflicting software drivers. Instead, the BtV architecture pioneers an approach for "packetizing" the multimedia data types so that they can be more efficiently processed within a single memory space. At the same time, the data types may now be centrally controlled and manipulated for improved performance and interactivity.
This feature has become increasingly important as Windows 95 has migrated multimedia to a new software architecture with APIs that encourage fast-paced intermixing of data types. It provides a link between Microsoft's DirectDraw and DirectVideo graphics and video APIs for video-over-graphics chroma-keying and between the DirectSound and DirectVideo sound and video APIs for precision lip synchronization and more extensive sound-effects queuing.
The chip set is the only way that you can display true-color video in a 1-Mbyte frame buffer. The chip allows you to do this because it packetizes the video stream in its smaller, native YUV format and performs the scaling in the back-end PACDAC. The packet-style data flow from the BtV MediaBuffer to the PACDAC allows the graphics and video to utilize the entire serial bandwidth of the MediaBuffer's serial port. The graphics and video data are separated logically within the physical MediaBuffer, allowing each to reside in its own color space. The PACDAC then performs the necessary color space conversions and scaling needed to generate the analog RGB outputs. The device costs $75 in sample quantities.
Brooktree Corp, San Diego, CA. (619) 452-7580
bq2031 lead-acid IC
The bq2031 combines all of the necessary control elements for safe constant-voltage or -current charging in both cyclic and floating (maintenance) charge modes. Its pulse-width-modulated regulator is well-suited to high-efficiency switch-mode designs. You can configure the regulator for linear or gated-current applications. By compensating voltage thresholds used during constant-voltage charging, the device extends battery life over a wide temperature range.
The 16-pin IC features an LED-output display of charge status and fault conditions. Via pin strapping, the user selects among three charging algorithms (two-step constant voltage, dual-level constant current, and constant-current pulse), two maintenance modes, and four charge-termination criteria (maximum threshold voltage, second-difference-of-cell voltage, minimum cut-off current, and maximum time-out). The device also inhibits charging until battery voltage and temperature reach configured limits. $4.80 (1000).
Benchmarq Microelectronics Inc, Dallas, TX. (214) 437-9195
INA116 instrumentation amp
In addition to a 3-fA (typical) input bias current, the INA116 instrumentation amplifier includes onboard guard drives for each input. The drives minimize unavoidable circuit-board leakage, which can adversely affect accuracy. The low bias current reduces the circuit-voltage-offset errors and noise contributions due to bias current down to negligible values. The INA116 maintains this low bias current even at temperatures as high as 125°C, and the bias current is independent of input common-mode voltage as well as power- supply voltage. Applications of this amplifier include pH, conductivity, leakage current, and electric-field measurement. $6.95 (1000).
Burr-Brown Corp, Tucson, AZ. (520) 746-1111
IMP50E10 user/field-programmable analog circuit
The Electrically Programmable Analog Circuit (EPAC) is the analog counterpart to the digital FPGA. This 5V IC allows users to configure analog functional blocks as needed, reducing time to market and development costs. The IMP50E10 provides general-purpose performance suitable for signal-conditioning circuits in data acquisition, data conversion, and sensor interfacing. On-chip blocks include PGAs, comparators, multiplexers, DACs, track and hold, and filters. You can even configure devices dynamically to meet real-time changing needs.
Along with the EPAC, a Windows-based development system simplifies device configuration and evaluation and specification of parameters. $20.90 (500); the development system costs $1495.
IMP Inc, San Jose, CA. (408) 432-9100
MAX471 current-sense amp
This current-sense amp connects directly in series with the high side of a battery-to-measure charge and discharge (bidrectional-current flow), which is critical for proper battery management. The internal sense resistor eliminates the need for an external milliohm resistor. In addition, high-side sensing means that the circuit designer does not have to interfere with critical ground paths.
The architecture provides a 30-mOhm internal sense resistor, followed by a differential amplifier. The topology results in a reading accuracy within 2% over the temperature range. The eight-pin IC operates from 3 to 36V and consumes 100 µA in active mode. $1.95 (1000). Maxim Integrated Products, Sunnyvale, CA. (408) 737-7600
LMC698x intelligent-battery systems
The three devices in this family integrate four key functions for batteries, regardless of cell chemistry (NiCd, sealed lead acid, LiMH, or Li-ion). The devices calculate state of charge (fuel gauge), control charging rate, store the history of the intelligent battery for more efficient operation by the host computer, and communicate critical information between the battery pack and the host system. Each mixed-signal IC contains four major functional blocks: analog signal conditioning, digital control circuitry, firmware, and user-application software.
The intelligent-battery system consists of the LM6980 data-acquisition system for monitoring key parameters and performing fuel-gauging and charge control; it works with the LMC6984 embedded controller for the Microwire serial bus or the LMC6988 battery controller for the system-management bus. $7 (10,000).
National Semiconductor Corp, Santa Clara, CA . (408) 721-5000
32P4915 PRML read-channel ic
This IC provides a 140-Mbps partial-response, maximum-likelihood (PRML) read channel using primarily analog circuitry. Although it implements a Viterbi detector, the device does not do so digitally; instead, it uses an analog-based design and sampled analog signal-processing techniques. The resulting IC is smaller and uses less power than a conventional digital implementation, yet provides comparable bit-error-rate performance.
The PRML read channel also includes analog filtering, precision T/H circuitry to implement the analog Viterbi detection, and an adaptive five-tap FIR filter. The adaptive capability of the filter reduces the number of programmable registers to 17 from 64. The 100-lead TQFP device is $16 (1000).
Silicon Systems Inc, Tustin, CA. (714) 573-6000
SP503 serial transceiver
The SP503 meets the hardware (Level 1) requirements for serial-interface applications. Under user-software control, it configures internal arrays to provide seven line drivers and receivers that meet electrical and performance specifications for RS-232C, V.35, RS-422, RS-449, and EIA-530 standards. This arrangement eliminates the need for multiple discrete drivers and receivers, jumpers, or switches, along with power supplies and their switching circuitry. The 5V, 80-pin MQFP device replaces circuitry that requires considerably more board space (1 in. vs 7 to 8 in.) and power. It provides flexibility in applications. $14.50 (1000).
Sipex Corp, Billerica, MA. (508) 667-8700
FLEX 10K PLDs
The high-density FLEX 10K SRAM-based PLDs offers embedded array blocks (EABs) for use as memory and other lookup-table-based functions in addition to standard logic elements (LEs). Each EAB offers 2048 bits of memory that can be configured in 2048×1, 1024×2, 512×4 or 256×8 organizations and offer 50-MHz operating speeds. You can combine multiple EABs to create larger memory structures. The EABs can be used as standard synchronous or asynchronous RAM, dual-port RAM, FIFOs, multipliers, ALUs, and other special functions. For example, a 4×4 multiplier requires one EAB and operates at 50 MHz. An 8×8 multiplier uses four EABs and 15 LEs and operates at 30 MHz. Other example constructs include a 256×8 FIFO requiring one EAB plus 42 LEs operating at 50 MHz and an 11-tap FIR filter requiring six EABs plus 88 LEs and operating at 50 MHz.
Currently the FLEX 10K50 is available offering 50,000 usable gates including 20,480 memory bits in 10 EABs. The device also has 2880 LEs, contains 3184 registers, and provides as many as 310 user I/O pins. It costs $995. Other members of the family will be brought out during 1996 and will provide from 10,000 to 100,000 gates.
Altera Corp, San Jose, CA. (408) 894-7000
Fast Flash 5V flash PLDs
The FastFLASH XC9500 PLD family uses a 5V flash technology that is in-circuit reprogrammable without requiring a 12V programming voltage. Although other EEPROM-based PLDs offer 5V in-circuit programming, they don't offer the 10,000 program/erase cycles available from this PLD family. The large number of cycles makes these devices suitable for applications requiring frequent field upgrades and reconfigurations. To make the in-circuit programmable feature most useful, the device also offers pin locking capability that will normally accommodate fixed pin assignments. Even when major logic changes must be made internally, the device doesn't require pc-board-layout changes. Pin locking is accomplished by using a fully populated switch matrix, a wide-function block fan-in, and a flexible function block-wide product term allocation. To aid manufacturing and test operations, the device provides an IEEE 1149.1 boundary scan implementation supporting the following JTAG instructions: Preload/Sample, Extest, Bypass, Usercode, IDcode, Intest, and HighZ. The PLD family offers nine devices with 800 to over 12,000 usable gates and pin-to-pin propagation delays as low as 5 nsec. The XC95108 with 108 macrocells and 2400 usable gates costs $17.50 (OEM). Other members of the XC9500 family are scheduled to become available during 1996.
Xilinx Inc, San Jose, CA. (408) 879-4651
ColdFire RISC architecture
ColdFire, a variable-length-instruction RISC architecture (VL-RISC), has evolved from the 68000. VL instructions help to attain higher code density. The company achieved the architecture's reduced size (approximately 55k transistors) by eliminating infrequently used M68000 instructions and by optimizing the pipeline. (ColdFire continues to use the M68000 programmer's model.) The vendor designed the device's hardware implementation from scratch using a tool-driven, synthesized design approach. ColdFire belongs to Motorola's FlexCore program, which allows you to design processors. In addition, the company offers standard products based on the ColdFire architecture.
ColdFire has a four-stage pipeline that consists of two subpipelines: a two-stage instruction-prefetch pipeline and a two-stage operand-execution pipeline. A 12-byte FIFO-instruction buffer decouples the two pipelines. The prefetch pipeline calculates the next instruction address and fetches 32 instruction-data bits. The operand pipeline has a dual-read-ported-register file feeding an arithmetic/logic unit.
A modular, standard bus architecture separates the CPU core from on-chip peripherals. The core communicates with on-chip memories using a tightly coupled processor bus, the KBus. This bus lets the core perform a 32-bit fetch from internal memory in a single clock cycle by pipelining the address and data. A controller interface on the KBus indirectly attaches the core to user-selectable cache, ROM, and RAM modules.
Another ColdFire bus, the MBus (master bus), offers centralized arbitration. A special module connects the MBus to the KBus. The SBus (slave bus) interfaces to standard on- and off-chip peripherals and attaches to the MBus through a system bus controller. The interesting feature of the buses relates to silicon efficiency: If you don't need a bus, you can remove it and eliminate the overhead.
A core-based design may arise where there is no external address/data bus. For these situations, ColdFire has an integrated-debug-module interface, which allows you to perform full-featured emulation. The interface supports three modes: real-time trace, which reflects the processor's status and indicates events such as instruction completion and monitor of change-of-flow target addresses; real-time debug, which supports three hardware breakpoints: PC relative, operand address, and operand data; and nonreal-time debug, which is similar to background-debug mode on current 683xx products. You can use a three-pin serial interface in this mode to read register contents, generate an infinite priority interrupt, and force the CPU to halt.
Motorola, Austin, TX. (512) 891-6820
6x86 processor
Although Cyrix's 6x86 is still Windows- and Pentium-pin-compatible, the company used computer-architecture techniques that were new to the x86 processor. The company implemented these techniques, including register renaming and out-of-order completion, to eliminate data dependencies and resource conflicts. The 6x86 transparently performs register renaming by mapping eight logical x86 registers onto any one of 32 physical registers.
The 6x86 contains dual seven-stage integer pipelines plus a separate floating-point pipeline. The dual pipes let the processor decode, issue, and execute two instructions per cycle without restrictions for most instructions. Out-of-order completion takes place in the last two stages of the pipeline (execution and writeback). To simplify the out-of-order logic, the 6x86 does not use a result queue. An out-of-order instruction in one of the pipelines may stall the entire pipeline because one waits for the other to catch up. The instruction decoder tries to dispatch instructions to the two pipes in a manner that minimizes stalls, however.
The 6x86 also contains performance-enhancing branch prediction. The company claims branch-prediction accuracy of approximately 90%. (The two extra pipeline stages increase a mispredicted branch penalty to five cycles. The extra pipeline stages may help Cyrix increase clock frequencies, however.) A branch table buffer (BTB) contains two history bits and an address for each of the 256 branch targets. Conditional branches result in a BTB check for the branch instruction's target address. If the check results in a BTB hit, the processor checks the history bits associated with the address to determine if the program should take the branch. The 6x86 also has an eight-entry return-address stack that stores an address when a subroutine is called. This process allows the processor to predict subroutine return addresses.
The 6x86 contains a 16-kbyte, four-way set-associative unified cache (primary data cache and secondary instruction cache) that is dual-ported to allow two simultaneous fetches, reads, or writes. A 256-byte, fully set-associative instruction-line cache comprises the processor's primary instruction cache.
In addition to the traditional x86's memory-management unit, the 6x86 has a novel variable-sized paging mechanism. This mechansim allows software drivers to map address regions between 4 kbytes and 4 Gbytes and to increase performances in RAM-intensive applications, such as video graphics and desktop publishing.
The 6x86 runs at an initial clock speed of 100 MHz and costs $450 (1000). Cyrix plans to introduce 120-, 133-, and 150-MHz versions by the year's end.
Cyrix Corp, Richardson, TX. (214) 968-8387
Pentium Pro Processor
Intel's Pentium Pro (PPro) designers started from scratch on this microprocessor: The PPro barely resembles the Pentium or any x86 processor. With a single, decoupled 12- to 18-stage pipeline, the PPro trades less work per pipe stage for more stages. This architecture translates to higher clock frequencies.
Three independent engines comprise the PPro: fetch/decode, dispatch/execute, and retire. The fetch/decode engine converts instructions into one or more micro-operations (µops). µops improve performance by representing fixed-length, fixed-field, easy-to-execute operations. You can individually schedule the µops, which facilitates the out-of-order execution of instructions within the PPro.
After the decoder creates µops, it sends them to a 40-deep reorder buffer (ROB). The µops then await dispatch to the execute portion of the pipeline. At this point, the µops either are ready for execution or are waiting for data from a memory access or a result from a previous µop. To avoid register dependencies, the PPro performs renaming: Extra registers represent the x86's programmer-visible registers. The dispatch/execute engine queues ready-for-execution µops within a 20-entry, distributed reservation station. The PPro determines the data flow by analyzing which µops are dependent on each other's results. The device creates an optimized schedule of µops. The processor dispatches µops from anywhere (or any order) within the reservation station.
The PPro speculatively executes and returns these µops to the ROB, where the retire engine evaluates them. Although the PPro executes µops (or instructions) out of order, the device must complete the instructions in the original program order. Furthermore, speculative execution implies that the device executes some instructions that never retire. This situation occurs if the device mispredicts a program branch. When the PPro encounters a mispredicted branch, it must flush its deep pipelines and remove µops from the ROB. To minimize the potential of a mispredicted branch, Intel designers souped-up the PPro's branch-prediction mechanisms. The designers increased the branch target buffer to 512 entries and added extra history bits to provide more intelligence to the prediction algorithm.
The PPro's package contains a 256- or 512-kbyte, nonblocking level 2 (L2) cache. The L2 cache connects to the PPro via a dedicated 64-bit-wide bus that is driven at full CPU-core speed. Furthermore, the PPro and cache are designed to support multiple, overlapped requests. Other new features of the PPro include its 36-bit address bus and a glueless multiprocessor interface for up to four CPUs.
The PPro is available with a mixture of frequency and L2 cache-size options. A 150-MHz PPro with a 256-kbyte cache costs $974 (1000); a 200-MHz processor with a 512-kbyte cache sells for $1989 (1000).
Intel Corp, Folsom, CA. (800) 628-8686
UltraSPARC µP
UltraSPARC is the first silicon version of SPARC V9. SPARC V9 maintains upward binary compatibility with SPARC V8. The specification also extends the architecture with support for 64-bit virtual addresses, integer data sizes up to 64 bits, and 32 double-precision, floating-point registers (up from 16). SPARC V9 also supports speculative loads, which don't take a fault if accessing an out-of-range variable. V9 defines a hardware mechanism that compilers can take advantage of to streamline the prefetching of data and instructions.
UltraSPARC includes special graphics instructions, the Visual Instruction Set (VIS), that are not in SPARC V9. VIS performs commands such as pixel expand, pixel packing, edge handling, partitioned add/multiply/compare, and align. VIS allows UltraSPARC to provide software support for video conferencing, 3-D visualization, animation, electronic publishing, video servers, and virtual reality. Block load/store commands perform 64-byte loads and stores directly to/from main memory. This feature lets the device bypass the cache memories and helps boost performance in network applications. Despite the performance benefits provided by VIS, Sun claims that these instructions only consume 3% of UltraSPARC's real estate.
The superscalar processor has a nine-stage pipeline in which the first two stages comprise the instruction fetch and decode. The designers added three stages to the integer pipe to make it symmetrical with the floating-point pipe. This architecture simplifies pipeline synchronization and exception handling; it also eliminates the need for a floating-point queue. The CPU's pipeline encompasses two integer ALUs, five floating-point graphic units, and a load/store unit. UltraSPARC can issue four instructions per clock to these nine functional units. Sun also includes a 2-bit dynamic branch-prediction mechanism, which is part of its prefetch unit. As the 16-kbyte instruction cache fills, the CPU uses two extra bits per instruction to tag on information related to the branch prediction for that instruction.
UltraSPARC uses data buffers to isolate the level 2 (L2) cache from the system bus. These buffers enable overlapping of system transactions and perform error detection/correction. The processor contains an on-chip L2 cache controller, and the system bus can run at one-half to one-third the processor frequency. Sun claims that instructions and data can pass between the L2 cache and the CPU at 2.6 Gbytes/sec.
The 143-MHz UltraSPARC costs $995 (1000). A 200-MHz version is in the works, and the company has proposed a 300-MHz UltraSPARC II.
SPARC Technology Business, A Division of Sun. Mountain View, CA. (408) 774-8119
The Thumb RISC Processor Architecture
Advanced RISC Machines' (ARM's) 32-bit ARM architecture implements a load/store architecture and a three-stage pipeline for single-cycle instruction execution. The ARM instruction set consists of only 32-bit fixed-length instructions, which the device can conditionally execute to minimize code size. In addition to the instruction set, the company has developed an optional macrocell, the Thumb module, which adds approximately 6% to the processor's die area. A Thumb-program compiler compresses the ARM's 32-bit instructions and stores them as 16 bits. This compression typically results in a 30% improvement in code density. At runtime, the Thumb module, residing within the instruction pipeline, decompresses the 16-bit instructions back to the full 32-bit versions. Thumb performs the decompression using a small lookup PLA that directly decodes the 16-bit instructions.
To achieve their high-density code goals, designers imposed several limitations on the Thumb-supported instructions. For example, Thumb only supports 36 of the most common or most useful ARM instructions. This limit is necessary for the device to perform full-speed decoding with a small PLA. Thumb also limits program access to eight registers, compared with the original 31. Thumb does not support conditional execution of instructions, but uses a new branch-on-condition instruction. Finally, Thumb does not support several system-level functions, such as memory-management-unit configuration and exception handling.
Despite Thumb's inability to support the preceding instructions and operations, a Thumb-equipped processor can still execute 32-bit and the 16-bit code; the only restriction is that the two instruction sets cannot be intermixed. So, if you still need to use Thumb's unsupported instructions, you can implement the 16-bit code to make subroutine calls to the separately compiled 32-bit code. This minor inconvenience more than makes up for the increase in code density that Thumb provides.
Advanced RISC Machines, Cambridge, UK. +44-1223-400440
MPC860 PowerPC-Based Communications Controller
Motorola's MPC860 Quad-Integrated Communications Controllers (PowerQUICC) are a family of single-chip microprocessors for the data-communications and internetworking markets. These µPs integrate a PowerPC core, a memory controller, a RISC-based communications processor module (CPM), and four high-bandwidth serial-communications channels.
The CPM controls the serial communication controllers (SCCs), transfers information to handle serial-channel interrupts, and performs built-in protocol processing functions. It controls either two or four SCCs, two serial-management controllers (SMCs) that can act as UARTs or transparent channels, one serial-peripheral interface (SPI), and one I2C port. The SCCs interpret and process communication protocols. The SMCs perform framing and serial interface tasks in ISDN-type applications. The SPI and I2C enable synchronous communication between the 860 and system components. The CPM also includes 16 serial DMA controllers, four general-purpose timers, and a multiply accumulate (MAC) function.
The system integration unit (SIU) controls a special memory controller for glueless connection to most types and widths of DRAM, EPROM, flash memory, EEPROM, and SRAM. This memory controller is user-programmable and is similar to a microcoded machine. Externally, its interface provides you with two general-purpose lines that you can assert and deassert on a one-quarter clock-cycle granularity. To provide this granularity, the MPC860 has two clocks running: the system clock and the system clock shifted by 90°. This clock shift essentially provides the same effect as doubling the clock. Motorola also offers a software-analysis tool that lets you create waveform outputs and learn how to control your system's memory. The 860's SIU also has an integrated PCMCIA 2.1 controller and a real-time clock. Depending on the configuration, the 25- and 40-MHz 860s cost $70 to $87.50 and $105 to $122.50, respectively (10,000).
Motorola Semiconductor Products Sector, Austin, TX. (800) 845-6686
Lsim Power Analyst
Power Analyst lets you determine power and current distribution in your chip. The tool's transistor-level analysis has accuracy close to that of Spice but at speeds more than 1000 times faster than Spice. Power Analyst employs a number of analysis techniques to evaluate the three common components of chip-power dissipation: switching, dynamic short circuit, and static short circuit (leakage). Power Analyst is based on a Series-Parallel Switch (SPS) algorithm, which provides a transistor model that includes local parameters, such as input-slope-dependent delay modeling, as well as global parameters that are a function of how a circuit is using a transistor. The tool models transistor loads as distributed RC networks.
You use Power Analyst to simulate all three types of power usage on a chip. You can review both dynamic and static currents at a detailed level using a combination of graphical and textual information. Interactive diagnostic capabilities allow you to determine which blocks in a design are dissipating significant amounts of power at various times during chip simulation. For example, you can analyze peak currents by setting a breakpoint on a current peak. The program lists, in order of current drain, the blocks drawing the most current at that time. You can investigate static short-circuit currents, which may indicate a design problem, through the tool's ability to separate static and dynamic current drain. After you identify a problem, you can then modify the circuit to decrease power consumption and rerun the analysis to determine how effective the changes are in reducing power.
Power Analyst lets you know how much current is flowing in selected portions of your chip. For example, you can calculate peak current for each block and, using this information, design adequately sized VDD lines to prevent excessive IR drops. You can also calculate average currents to size power lines to avoid electromigration-induced reliability problems.
Mentor Graphics Corp, Wilsonville, OR. (503) 685-7000
VFormal Verification Tool
Formal verification is a technique used to compare two versions of a design to see if each is functionally equivalent. VFormal is a tool you use to perform a formal verification on VHDL designs. You can use the tool on any synthesizable VHDL construct at any level of abstraction. For example, you can compare the register-transfer-level (RTL) and gate-level representations of a design to see if the design has inadvertently changed during synthesis. In addition, VFormal also tells you where errors exist in the VHDL code. You can use it to detect problems such as redundant memories or registers, unused I/Os, dead-end states, asynchronous feedback problems (which may lead to unwanted oscillations) and nodes that never toggle or toggle just once.
VFormal uses rigorous mathematical methods to prove equivalence for all possible sets of inputs. The tool does this using a two-stage process. First, VFormal analyzes the design and generates complete representations of the logical functions in terms of Boolean equations. Second, VFormal compares the representations to prove equivalence. If the representations are not equivalent, VFormal tells you exactly how they differ. Unlike simulation, VFormal does not need test vectors to run. Simulation often requires new sets of test vectors for different levels of the design's hierarchy, because lower-level blocks may not be able to use high-level vectors. The generation of these vectors is time consuming. After initial simulation, you use VFormal in place of additional simulations to check different blocks.
You also use VFormal to check design changes caused by ECOs, design refinements, resynthesis, retargeting to a different technology, optimization and test circuitry insertion. Because it works hierarchically, when you make a change in your design, you need only use VFormal on the portions that have changed. Although VFormal's initial analysis phase takes about as long to run as the synthesis phase for the same design, comparisons using the tool are much faster. Coupled with no test-vector requirements, this means that you can functionally check your changed design very quickly.
COMPASS Design Automation, San Jose, CA. (408) 433-4880
V-System/PLUS Single-Kernel Simulator
Many designs include both VHDL and Verilog modules. Even if you do a design primarily in one HDL, you may want to include models written in another. Examples of this include reuse of existing blocks and use of a core developed by a third-party vendor. V-System/PLUS is a single-kernel simulator, which means that you can use it to cosimulate both VHDL and Verilog descriptions, along with hardware and C-language models, at any level of the design hierarchy. Using a single-kernel simulator means that you only have to worry about one user interface and a single event queue. Without single-kernel simulation, you need to run both VHDL and Verilog simulators on a common backplane. Backplanes need software to synchronize the two simulation processes, each process with its own event queue. The slowest simulator controls simulation speed. Backplane simulation of VHDL and Verilog may also compromise design capacity, because you need to load two simulators and the synchronization software into memory, leaving less memory available for the design database. If your design simulation exceeds this memory, the simulators have to page to the disk, significantly reducing simulation speed.
V-System/PLUS uses Direct Compile technology, which manages the complexity of the mixed simulation by resolving naming conventions and maintaining design hierarchy. Direct Compile also generates machine-independent object code. You can compile a design on a workstation at your office during the day, for example, and then take the same design home for work on your PC. V-System/PLUS has easy-to-use graphical-debugging and signal-trace capabilities. You can probe into either a VHDL or Verilog module, set breakpoints, and single-step through the simulation, regardless of which HDL generated the module. The tool identifies each system block with a symbol indicating whether it is VHDL or Verilog. Being able to use the same tracking and debugging techniques for either type of HDL module simplifies design development.
Model Technology Inc, Beaverton, OR. (503) 641-1340
DesignBook Tool Suite
The rising complexity of designing chips requires you to efficiently apply and manage the tools a typical user has at his/her disposal. DesignBook is a suite of high-level design-automation tools that works with your existing tools. With DesignBook, you capture more than just the design description: You capture the full design specification, including function, implementation constraints, vectors to validate the design, library cell references and characteristics, and documentation. The tool set then generates VHDL or Verilog code, a tool script, and design checks tailored to your tools. You use DesignBook for a variety of digital chip designs, including cell-based, gate array, and programmable logic (FPGA and CPLD).
Your input to DesignBook consists of a mix of textual and graphical information. The tool set includes a graphical editor for state-machine design, a block-level editor for dataflow diagrams and parameterized library structures, an equation editor for simple combinatorial expressions in HDL form, and an HDL editor. A stimulus-and-timing waveform editor and a test-bench database allow you to include constraint information for the design. When you finish your design entry, the tool suite generates HDL code tailored to your simulation or synthesis tool and the target silicon technology. DesignBook's Simulation Commander takes care of vector formatting details when it launches your choice of simulator. Synthesis Commanders drive various synthesis tools in an optimum fashion by tuning the HDL code, scripts and constraint files according to your design intent, implementation tools, and target technology. A waveform editor window displays simulation or synthesis timing information. DesignBook currently supports synthesis tools from Exemplar and Synopsys and simulation tools from Model Technology, Mentor, and Cadence.
Escalade Corp, Santa Clara, CA. (408) 654-1600
INCA Simulator
The Interleaved Native Compiled-code Architecture (INCA) is a software architecture for concurrently executing multiple simulation approaches. The simulation approaches include multiple language (VHDL and Verilog), multiple levels (behavioral and gate), multiple paradigms (event-driven and cycle-based) and mixed-signal (digital and analog). You can use INCA for any electronic-design simulation, from individual chips to system simulations of pc boards and boxes. The architecture interleaves the code streams during simulation, resulting in the use of a single simulation engine and no cosimulation penalties. INCA is an extension to the Native Compiled Code (NCC) approach to language-based simulation, which offers performance and capacity advantages over interpreted or compiled C approaches. NCC simulation also requires significantly less memory then other techniques, particularly if they require multiple simulation engines. The technique is based on the direct generation of native machine code for the RISC-based workstation on which it runs. Because it bypasses the intermediate translation steps needed by interpreted and compiled code simulators, NCC-based applications show significantly improved throughput.
With INCA, optimizing compilers for each input language or format creates a sequence of instructions. The software then interleaves the instructions to create a single, contiguous code stream representing the specific blend of simulation languages and techniques that the host processor executes. A mix of Verilog and VHDL allows you to simulate designs represented primarily in one language, but with embedded cores or other blocks written in the other HDL. By combining event- and cycle-driven simulations of a system, you can use the event-driven simulator, for example, on asynchronous portions of the design and the more efficient cycle-based simulation on the complex synchronous portions. This results in a more efficient simulation for many complex designs.
Cadence Design Systems Inc, San Jose, CA. (408) 943-1234
CAMCAD for Windows Translator Tool
CAMCAD for Windows is an interactive, universal translation tool for 2-D graphic files, such as Gerber, DXF, and HPGL. You use CAMCAD for pc-board mechanical and layout design. One of the special features of CAMCAD is that it can create a drawing composed of multiple drawings, each with its own data format, units, and scale factor. The multifile and multidocument interfaces (MDI) of CAMCAD give you the flexibility to create a complex drawing composed of data read from drawings in different formats. CAMCAD stores the graphics files that it reads in their native coordinates and formats. This property lets the tool translate between graphics formats without any translation errors. CAMCAD supports all Windows plot and print drivers, allowing you to produce checkplot drawings on a laser printer for review before generating time-intensive, large-scale plots. With clipboard and bitmap support, CAMCAD also lets you output graphic files into Windows-based word processors and desktop-publishing applications, providing the basis for easily produced design documentation.
Using its MDI feature, the basic CAMCAD module reads Gerber, HPGL, and DXF files and lets you view files composed of multiple formats. A print module gives you the ability to access and use standard Windows drivers and provides Gerber-to-laser printer support. Other optional modules give you editing and expanded read and write capability. The interactive graphic editing module lets you highlight, edit, change, and add elements to drawings. Another module lets you input drill and route files for pc boards. Still other modules let you output mechanical graphics data to popular pc-board design systems, including those from PADS Software, PCAD, Protel, Accel, Redac, OrCAD and Mentor Graphics. Finally, there are additional modules for outputting data in DXF, Gerber, HPGL, or IGES format.
Router Solutions Inc, Newport Beach, CA. (714) 721-1017
BoardQuest Board-Level Design Environment
BoardQuest is an engineering environment for designing high-speed pc boards. You use BoardQuest from prelayout exploration to final layout, based on constraints obtained from various performance analyses. Then, after layout, you can verify whether your pc board has met all its original design criteria. Included in BoardQuest's planning capabilities are exploration of conceptual and architectural design alternatives; simultaneous logical and physical design; ASIC buffer selection; prelayout interconnect strategies; floorplanning, component placement, and critical-signal routing; and preliminary estimates of board area and component groupings. Although other tools can perform these design activities, BoardQuest integrates all of them into a single EDA environment.
BoardQuest works with a number of Cadence's performance domain tools such as SigNoise for signal integrity analysis, Thermax for thermal analysis, and EMControl for electromagnetic-compliance checking. Using the results from these and additional timing analyses, you derive performance-driven constraints to drive the floorplanning of and the component placement and routing on a pc board. BoardQuest includes a number of features to help with your design details. For example, you can automatically create terminators on single- or multiple-board systems based on analysis of the component interconnects. BoardQuest's termination synthesis predicts when to use terminators and determines the proper termination scheme to use for a specific design. Using the "what-if" analysis capability of BoardQuest, you can answer questions such as: Where should I place a high-performance microprocessor to avoid it overheating itself or neighboring components? and How can I decouple my design to meet signal integrity criteria with a minimum impact on board area? How much clock cycle time should I budget for ICs and how much for board interconnect?
Cadence Design Systems Inc, San Jose, CA. (408) 943-1234
Tornado embedded software development tool suite
The Tornado embedded-software development tool suite from Wind River Systems combines powerful graphical tools with minimal target resource overhead. It allows full access to its tool suite regardless of the link between the development system and the target system. In addition, it provides a framework that allows integration of third-party tools into the suite. Tornado runs under Unix, Windows 95, or Windows NT and works with the VxWorks operating system.
One key to Tornado's capabilities is its small run-time agent. Wind River has abstracted all the debugging functions that must be on the target system into a scaleable agent for VxWorks. The tool set can then use any available communications channel to interact with the agent. This flexibility allows the full set of Tornado tools to be available for debugging the target system, regardless of the target-to-host link.
Tornado also offers an API that allows third-party and customer-generated tools to work within the Tornado framework. By conforming to the API, these additional tools will automatically work with other tools in the framework, sharing data, graphical interfaces, and target connection. The API makes operation of these tools independent of the target architecture and host-to-target link.
The product also comes with extensive on-line technical support. That support is available over the Internet, and Tornado uses that link to simplify support help. Users can fill out an assistance request form, append data and configuration files as needed, then send the entire package to technical support all from within Tornado.
Wind River Systems, Alameda, CA. (510) 748-4100
SPOX in multiprocessor version
SPOX-MP is an upward-compatible version of the popular SPOX operating system version 2.0, but adds facilities to simplify development of multiprocessor applications. SPOX-MP works with any multiprocessor topology, including master-slave configurations, attached multiprocessors, and hypercubes. It is initially available for the TMS320C4X DSP family from Texas Instruments and the Analog Devices' SHARC family.
SPOX-MP uses a device-independent interprocessor communication (IPC) mechanism within the operating system that handles dynamic data and message routing. This mechanism allows designers to move their applications from single-processor to multiprocessor configurations without altering their source code. Further, the hardware independence of the IPC insulates the application program from the multiprocessor topology.
Because SPOX-MP makes application software design independent of the hardware, programming for multiprocessor use becomes as simple as programming a single processor. All the designer needs to do is create the software as a collection of cooperating tasks, then assign those tasks to different processors in the system. The OS handles all other details.
To simplify software loading at boot time, SPOX-MP includes a flood-fill loader. The loader allows a single executable image to contain programming for all processors in the system. SPOX loads the image into the first processor's memory. That processor, in turn, sends the image to all connected processors, which fan out the image further until all processors have received their code.
Spectron Microsystems, Santa Barbara, CA. (805) 968-5100
Eaglei Toolset
The days of waiting for hardware to be ready before integrating code are over. The Eaglei Toolset's Virtual Product Console provides a link between hardware simulation and code development tools. The product provides simulation speeds from 1500 to 5000 instructions/sec, fast enough for interactive debugging.
The hardware simulator incorporates both a proprietary Virtual Processor Software simulator and links to commercial EDA simulators. The Virtual Processor handles register- and interrupt-level simulation of the processor. The commercial simulators, such as Vantage Optimum and ViewSim VHDL, handle RTL, gate-level, and hardware model descriptions for the remaining hardware.
Users perform code development on their standard development tool platform. The Virtual Product Console then links the development tool set to the hardware simulation, allowing users to debug code using familiar tools on simulated hardware. The application code, written in high-level C, runs on the development-tool host workstation while the hardware simulation runs on the EDA tools.
The Virtual Product Console will work in a networked configuration. This networking capability allows the tool to simulate multiple processors simultaneously, each simulation running on a different host along the network. Hosts may be Sun, HP, or IBM PC (Windows NT) platforms.
Eagle Design Automation Inc, Beaverton, OR. (503) 520-2300
Photon micro-GUI
Photon micro-GUI Embedded systems often have too few resources to provide a graphical user interface (GUI). The Photon microGUI solves that problem by using a microkernel design. The software consists of a small (<400 kbytes) graphical kernel and a team of cooperating processes. The kernel itself is sufficient to provide a basic GUI. The other processes enhance and expand the kernel's capability to achieve a full-featured windowing system.
Photon offers a rich library of controls that operate like the X-Window System widget set. It also offers a Motif-like window manger and a code-generating application builder. The application builder is similar to Visual Basic.
Photon is fully distributable and network transparent. If the kernel resides in an embedded system that has a LAN connection, then all the resources on the LAN are available to the system. Thus, a simple node in the system can provide a full-featured windowing GUI even if it is resource limited. It simply utilizes processes running on other nodes to supplement its operation. The transparency also allows users to move live applications from one node to another. In effect, you can drag an operating process from one screen to another without interruption.
QNX Software Systems Ltd, Kanata, Ontario, Canada. (800) 676-0566
Pereos 1-Gbyte tape drive
In an industry known for evolutionary capacity growth and a short list of accepted media types, Datasonix Corp chose a revolutionary micro-cassette to store more than 1 Gbyte of data with compression. The entire drive measures only 2 3/8×4×1 7/8 in. and can operate from 2 AA batteries or from 0.5W of power drawn through the mouse port of a notebook computer. Pereos is the first tape product that directly addresses backup needs in portable systems and offers an attractive price/performance profile for desktop users. The size and portability of the product could also make the product attractive in a variety of embedded system applications.
Pereos uses helical-scan-recording technology to store data on 2.5-mm tape. A four-head drum ensures that all data written to the tape can be immediately verified--eliminating the need for a separate verification pass. The tape stores data at an areal density of 175 Mbits/square inch, and the drive can achieve a transfer rate of 10 Mbytes/minute. The tape cartridge measures 0.85×1.18×0.2 in. and holds more than 81 ft of tape. The cartridges feature a native capacity of 600 Mbytes.
Datasonix sells Pereos as an end-user product for $499, including one tape cartridge, an ac power adapter, and software. The standard Pereos 2-D software includes conventional backup/restore capabilities, and the optional 3-D software includes robust file-management capabilities. Pereos connects to a PC via the parallel port.
Datasonix Corp, Boulder, Co. (303) 545-9500
CompactPCI passive backplane architecture
A derivative of the Peripheral Component Interconnect (PCI) local bus, the CompactPCI passive backplane specification targets industrial control and embedded computer applications. The spec, which was originally authored by Ziatech, recently received approval from the PCI Industrial Computer Manufacturers Group (PICMG). CompactPCI employs industry-standard mechanical components and connectors can operate in rugged environments. Electrically, the spec offers compatibility with desktop PCI, allowing the passive bus to provide a 32- or 64-bit data path and data transfers as fast as 264 Mbytes/sec. Moreover, designers working on CompactPCI products can use the same low-cost VLSI technology that is used in PCs.
CompactPCI specifies the 3U, Eurocard-sized format measuring 160×100 mm. The 3U format fills the need of embedded system designers for compact size and allows designers access to existing, industrial-quality enclosures and mechanical components. The spec also provides for expansion to the 6U format if required in the future. Moreover, 3U CompactPCI cards can be used in hybrid systems alongside other backplane technologies, such as VMEbus.
Ziatech has also introduced a family of CompactPCI cards and systems. The ZT 6500 single-board computer combines a Pentium processor, 48 Mbytes of RAM, 4 Mbytes of flash memory, and assorted I/O and communication ports for $2650. The ZT 6200 CompactPCI System sells for $4500 and includes the ZT 6500 card and an eight-slot enclosure. Available support boards include graphics controllers, graphics-capture boards, and I/O boards. Ziatech also offers the $3200 ZT 8906 Pentium-based STD 32 board that includes a bridge to three CompactPCI boards.
Ziatech Corp, San Luis Obispo, CA. (805) 541-0488
TeraDON 16-DSP ISA card
Designers working on multichannel telecommunications and multimedia applications can turn to the TeraDON board from Ariel Corp. Offering an aggregate 533 MFLOPS of number-crunching capacity, the board hosts 16 AT&T DSP3210 floating-point DSPs and 256 Mbytes of DRAM. The board also provides Signal Computing System Architecture (SCSA) and Multi-Vendor Integration Protocol (MVIP) interfaces that are being widely used to connect computer and telephony systems. A QuickRing interface provides an additional connection to high-speed I/O devices.
To cram 16 processors on a full-size ISA card, Ariel's engineers developed a proprietary mezzanine-card packaging technology called DON modules. Occupying approximately the footprint of a 3½-in. floppy, a DON module integrates four DSPs and 64 Mbytes of shared DRAM. The local buses of each DSP are combined to form the local memory bus and to provide access to off-module resources. The TeraDON board includes sites for four DON modules. All 16 DSPs on the TeraDON can run AT&T's Visible Caching Operating System (VCOS). The real-time, multitasking operating system can host multiple telephony or multimedia functions simultaneously. Moreover, Ariel and AT&T offer a comprehensive library of ready-to-run functions. Some of the applications for the $9995 board include implementing 16 modems, multichannel P*64 video conferencing, MPEG encoding, and text-to-speech synthesis on as many as 200 channels.
Ariel Corp, Highland Park, NJ. (908) 249-2900
RACEway switched-fabric interconnect
A plethora of applications ranging from video processing to radar/sonar to telecommunications can benefit from cost-effective, off-the-shelf VMEbus products. But despite VMEbus being the fastest, most robust standard bus available, the general-purpose backplane falls short of offering the transfer rates required in these applications. The RACEway switched-fabric interconnect scheme developed by Mercury Computer Systems brings 160-Mbyte/sec, point-to-point links to any pair of boards in a VMEbus system--the same type of switched, point-to-point links found in supercomputers.
RACEway has also been adopted as a standard by the VMEbus and Futurebus International Trade Association (VITA). RACEway transforms VMEbus from a single-transaction bus to a multiple-transaction switched fabric offering an aggregate throughput of 1.28 Gbytes/sec. The technology can be added to standard VMEbus connections by plugging a module onto the backside of the VMEbus P2 connector. Mercury offers RACEway in 4-, 8-, and 16-slot models. An ASIC is also available for implementation on VMEbus boards, and Mercury offers boards with integrated RACEway capabilities. Mercury's 16-slot ILK16 module can support eight concurrent data transfers at 160 Mbytes/sec. It also includes broadcast and multicast capabilities. The module offers a worst-case connection latency of 1.4 msec, which along with the concurrent data-transfer capability, serves real-time applications even better than standard VMEbus. The ILK16 starts at $6600.
Mercury Computer Systems Inc, Chelmsford, MA. (508) 256-1300
Baja4700 VMEbus CPU
Among the first VMEbus boards to support the PCI Mezzanine Connector (PMC), the Baja4700 single-board computer combines a 133-MHz R4700 Orion processor, 64 Mbytes of DRAM, Ethernet, dual PMC interfaces, and assorted I/O facilities. The 64-bit board meets the VME64 spec and includes a number of VME64 extensions including geographical addressing. The board will support 175-MHz processors when they become available.
The Baja4700 design was optimized for fast data transfers on and off board. Internally, a 200-Mbyte/sec synchronous local bus links all core subsystems. including the µP, memory, Ethernet controller, VMEbus controller, and PMC interfaces. The board uses buffering and DMA facilities to ensure that all subsystems can send and receive data at full rated speed. The Baja4700 can also sustain 70-Mbyte/sec memory-to-memory transfers with other boards.
Heurikon targets the Baja4700 board at communications applications such as bridges between WANs and LANs. Designers can use the dual-PMC sites to mix and match support for networks ranging from ATM to 100-Mbps Ethernet to FDDI to Fibre Channel. Moreover, the µP offers the compute power necessary to execute most communication protocols. Heurikon offers a variety of software support for the $5895 board, including the VxWorks real-time operating system and driver support for third-party PMC SCSI, WAN, and LAN modules.
Heurikon Corp, Madison, WI. (608) 831-5500