However, you can use Figure 1's much simpler circuit, which does not require full adders, if you need to detect only three conditions: no ones, one one, and two or more ones.
Design Ideas: February 1, 1996
In some cases, you may need to monitor the number of logic ones present on a set of signal lines. In the classic method to provide this monitoring function, the parallel-counter circuit that Reference 1 describes counts the number of ones on a set of N-1 signal lines, where N is a power of two.
However, you can use Figure 1's much simpler circuit, which does not require full adders, if you need to detect only three conditions: no ones, one one, and two or more ones.
Note: The condition in which ones are present on all but one of the signal lines corresponds to the second condition for complemented input signals. The circuit in Figure 1 is a 2-D array of two simple logic cells organized in a binary tree. A C cell ( Figure 2a) processes each pair of input signals. A D cell ( Figure 2b) processes the four output signals from each pair of C cells. The circuit decodes the two output signals from the last D cell in the tree (D7 in Figure 1) to indicate the condition describing the status of the input signals applied to the array.
Thus, an array of N/2 C cells and N/2-1 D cells can monitor N input signals. You can accommodate values of N other than powers of two by using two or more arrays and combining each pair into a single array with a single D cell. This circuit is economical to implement in an ASIC. The worst-case delay of approximately 2log2N gate delays is comparable with the delays of other decoding schemes. Using typical CMOS gate-array macrocells, the logic for processing 32 input signals has a complexity equivalent to that of a circuit using fewer than 100 two-input NAND gates. (DI #1820) Reference
1. Schwartzlander, E, "Parallel Counters,"IEEE Transactions on Computers, V C-22, No. 11, November 1973.