IBM Microelectronics’ new 0.35-µm CMOS 5X technology for advanced ASIC chip design provides 2.5V operation. The technology lets chips operate 20% faster than chips operating at 3.3V. You can use CMOS 5X to design low-power, battery-operated chips with as many as 1.6 million logic gates and as many as 748 I/O pins. The process technology provides six layers of metal--five for global wiring and one for local interconnect. This many interconnect layers let you shorten wiring paths in chip designs, helping you meet critical timing specifications.
CMOS 5X technology supports three types of I/O connections: 2.5V CMOS, 2.5V CMOS with 3.3V protection, and 3.3V low-voltage TTL. The company is currently developing support for other I/O standards, including pseudo-ECL (PECL), PCI, and Gunning transceiver logic (GTL). CMOS 5X also offers a variety of useful macro functions, including compilable SRAMs, register arrays, ROMs, FIFO buffers, adder/subtracters, multipliers, and a PLL with tuning bits to minimize jitter. The technology comes in several high-pin-count packages, including ceramic-column grid array (CCGA), which provides as many as 748 signal pins and 1088 total pins.
The technology works with the company’s own logic- and physical-design tools, as well as front-end design tools from well-known EDA vendors, including Cadence and Synopsys. You can begin working with CMOS 5X design kits today, and IBM is now accepting ASIC netlists.
-- by Jim Lipman
IBM Microelectronics, Essex Junction, VT. (802) 769-6109
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