Out in Front: February 1, 1996

SGS-Thomson has added a fully static, 3.3V, 486-processor core to the 0.35-µm HCMOS 6 ASIC library. The ST486DX core runs at clock rates from dc to 120 MHz with bus speeds set at one-half or one-third the processor clock. This core is a real 486DX-type design with an integrated 8-kbyte, unified instruction/data, write-back cache and a floating-point unit that automatically powers down when it’s not executing a floating-point instruction.

The ASIC 486 core also incorporates a system-management mode (SMM) for power management at the system level. Software activates the SMM through a system-management-interrupt instruction; a system-management-interrupt pin provides hardware activation of the feature. The system-management interrupt causes the CPU to start executing code in an isolated SMM memory space. The core µP also has a suspend mode that reduces power dissipation to less than 1% of the full operating power.

ASICs based on the ST486DX core are available in many IC packages, including PFQPs and pin- and ball-grid arrays (BGAs) with 84 to 304 pins or leads. The company is developing BGAs with as many as 480 leads. Prices and NRE charges depend on the number of gates in the ASIC, package style, and production volume.
-- by Steven H Leibson

SGS-Thomson Microelectronics, Phoenix, AZ. (602) 788-6228