Out in Front: February 1, 1996

Providing seven devices with 28,000 to 125,000 gates, the XC4000EX family from Xilinx extends the density beyond the previous 25,000-gate limit of its XC4000E device family. The new device family, although directly compatible with the previous family, offers significant architectural changes and performance improvements.

The new FPGA family offers approximately twice the routing resources for both long and short interconnects on the XC4000E family. These new routing resources minimize interconnection delays and maximize logic usage on the high-density devices. Three clock-signal network features are available on the new devices: Global buffers help maintain low clock skew across the device, edge buffers provide high-speed clocks for critical paths and high-performance modules, and FastCLK buffers maintain low skew for chip-to-chip communication. The new clocking plus improved I/O cells enable the device to offer 4-nsec setup and 6-nsec clock-to-output times. The device family also offers the VersaRing I/O interface providing pin-assignment flexibility. The feature helps you maintain fixed pin assignments even when you have to make internal logic changes. The devices also provide dedicated JTAG (Joint Test Action Group) boundary-scan logic, a necessity for most manufacturing test operations in high-pin-count ball-grid-array packaging.

You can configure the devices’ configurable logic blocks (CLBs) for logic operations or as a memory element. You can configure each CLB as 32 bits of single-port RAM; 16 bits of dual-port, high-speed, synchronous RAM; or logic functions. When you use the CLB as RAM, the CLB accommodates a 70-MHz write-cycle time. You can also use the CLBs to implement fast FIFO buffers, and you can use multiple CLBs to construct larger RAMs or FIFO buffers, trading logic capacity for memory as your design requires. When you use a CLB for logic, the new devices offer storage elements that you can use as either flip-flops or latches.

According to the manufacturer, the 100%-PCI-compliant devices deliver typical system speeds of 66 MHz. All of the new devices will be available in 3 and 5V versions. The 3V versions have 5V-tolerant I/O. The XC4028EX with 1024 CLBs and 28,000 usable gates is available now and costs $695 (100). The company expects prices to be less than $200 (10,000) by year’s end. The company also offers HardWire gate-array versions of the device. These versions cost $45 (25,000). When a design stabilizes, the HardWire version lets you reduce production cost without additional design or test-vector generation. Xilinx will release other members of the XC4000EX family during the remainder of this year and the first quarter of 1997.
-- by Doug Conner

Xilinx Inc, San Jose, CA. (408) 559-7778