Out in Front: February 1, 1996

Taking advantage of proprietary technology for optimizing the use of multiple FPGAs in emulation hardware, Virtual Machine Works has introduced its first product, the VirtuaLogic Emulation System. VirtuaLogic provides emulation for chips implementing more than 100,000 logic gates for substantially lower cost than other systems with similar capabilities. The system provides as many as 1.35 million usable gates of emulation and supports single-chip and multichip IC systems. It provides as much as 16 Mbits of memory for emulating embedded memories in your design. It also offers 3072 bidirectional I/Os for interfacing with the target system. Emulation speed ranges from 500 kHz to 2 MHz, which is orders-of-magnitude higher than logic-simulation techniques can obtain.

At the heart of VirtuaLogic is Virtual Machine Works’ VirtualWires. This technology uses an interconnection and resynthesis process that maps the logic design being emulated into a functionally equivalent design that, according to the company, maps into what appears to be one large FPGA and various SRAMs. The large virtual FPGA is equivalent to the sum of the smaller FPGAs that go into the VirtuaLogic Emulation hardware. Virtual Machine Works claims that the compilation of many small FPGAs into one virtual large unit results in a system that costs less and is easier to use than are traditional emulation systems.

The VirtuaLogic Emulator hardware comes with the VirtuaLogic Compiler and VirtualProbe Analyzer software. Without user intervention, the VirtuaLogic Compiler compiles a Verilog gate-level netlist as input into a form suitable for emulation. You need not remodel any internal circuit blocks, such as latches, gated clocks, internal PLLs, or multiported memories. Virtual Machine Works asserts that the compiled design is free of timing problems that may occur with other emulation systems and that the emulated design behavior is cycle-accurate to simulated design behavior. The system provides a Virtualized Simulation Model of your design that you can use with a simulation testbench to validate the design early in the compilation. With the VirtualProbe Analyzer and an HP 16500B logic analyzer, you can probe, display, and analyze as many as 1880 internal signals for debugging your design.

Virtual Machine Works will begin shipping the VirtuaLogic Emulation System in May. The system supports libraries from AT&T, IBM, LSI Logic, Motorola, NEC, Texas Instruments, Toshiba, and VLSI Technology. Prices start at $125,000, including the VirtuaLogic Emulator hardware and the VirtualProbe Analyzer and VirtuaLogic Compiler software modules, which run on Sun workstations. The HP 16500B logic analyzer costs approximately $50,000. Virtual Machine Works is planning support for register-transfer-level (RTL) and VHDL netlists this year
-- by Jim Lipman

Virtual Machine Works, Cambridge, MA. (617) 621-1700