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Design Ideas: February 15, 1996

FPGA configures simple BCD adder

Chris Jones
Cypress Semiconductor
San Jose, CA


thumbnailOften, the easiest way to execute a calculation with BCD operands is to convert the BCD inputs to binary numbers, do the calculation in normal binary fashion, then convert the binary result back to BCD notation. However, for some calculations, such as addition, it can be easier and more efficient to add the BCD numbers directly, without using binary conversions. The block diagram in Figure 1 shows how to implement a BCD adder in an FPGA.

The two BCD inputs, A and B, are both 12-bit operands that represent a decimal number between 000 to 999. You first add these two operands with a 12-bit binary adder to generate the sum E and the three carries C4, C8, and C12 from the add operation. You then adjust this first adder result by adding 6 (0110) to each group of four bits. Then combine the result (F) of this addition and the three carries D4, D8, and D12 with the result of the first addition to generate the final result.

Two four-bit incrementers for the two upper BCD results of the first result are also required. To select the least-significant BCD digit of the final, correct, sum, use the logical OR of carries C4 and D4. If either C4 or D4 is a logic one, then the BCD digit from the second adder is the correct result. Similarly, you take the logical OR of C8 and D8, and use the result to select the second BCD digit; and the logical OR of C12 and D12 selects the most-significant BCD digit.

thumbnailFigure 2 gives a simple example: the addition of 568 and 379, which equals 947. Six is the magic number for adjusting the result in BCD addition, because the difference between base 16 and base 10 is six. You need to add 6 to each BCD digit to account for skipping over the six unused representations from 1010 to 1111; that is, to transform a result from the forbidden range into the valid range. The incrementers account for a necessary carry that the first adder does not generate, but that the second adder does. Implemented in a Cypress CY7C382 1000-gate FPGA, this method for effecting BCD addition uses less logic and is faster than the brute-force method of converting to and from binary format. (DI #1825)



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