Electronic Design Automation: February 15, 1996

Windows-based PLD-design tools. Until March 31, 1996, the PLDesigner-XL Prodigy, which covers design synthesis, schematic interfaces for OrCAD and Viewlogic, EDIF 200 input, and functional simulation, costs $995 on the PC (from $2250). PLDesigner-XL Professional, which adds automatic-multiple-device partitioning, has been reduced from $4250 to $1995. With device-fitter and netlist modules for PLD, CPLD, and FPGA devices, PLDesigner-XL Professional costs $3995, from $8745. Minc Inc, Colorado Springs, CO. (719) 590-1155.

High-frequency design tool runs under Windows. With the help of IV/PC EDA software, you can use your Windows-based PC for high-frequency circuit design. The software provides a schematic editor, a multiple-circuit simulator, component libraries, analysis presentations, and design tools for RF and microwave circuits. It comes in á la carte modules or prepackaged design suites covering linear- and nonlinear-frequency domain and transient-time- and convolution-time-domain simulations. It runs on 486- and Pentium-based PCs under Windows 95 or Windows NT V3.51. Prices start at $8000. Hewlett-Packard, Santa Clara, CA. (800) 851-1170.

64-bit PCI bus models work with Verilog/VHDL synthesis. The 64-bit, silicon-proven source code is fully compliant with the PCI SIG 2.1 specification. Offered in both Verilog and IEEE 1076 VHDL versions, the modifiable source code is available under a single-fee, perpetual-site license. Prices start at $15,000 for either VHDL or Verilog target source code. Logic Innovations Inc, San Diego, CA. (619) 455-7200.

Development system works with PLDs. All of the vendor’s PLDs can now be programmed with Data I/O Corp’s Windows-based Synario development system. The package bundles the development system with the vendor’s fitters and supports design entry by schematics, ABEL-HDL descriptions, and state tables. Options include VHDL synthesis and a timing simulator for post-fitting verification. $895 for the basic entry package, $1195 for the VHDL-synthesis option, and $1995 for the timing-simulation option. Atmel Corp, San Jose, CA. (408) 441-0311.

Chip connects with the Internet. Easily customized using microprocessor and logic cores, a single chip brings Internet connectivity to a range of consumer products. The device is based on NetCore blocks, including the MiniRISC microprocessor. It also includes Oak digital-signal-processing, communications, video, audio, and bus-interface cores. Communication cores include V.34 phone, cable, and satellite modems, and Ethernet, ISDN, and ATM functions. Video cores cover VGA, MPEG 1 and MPEG 2 video decompression and NTSC and PAL encoders. The audio cores comply with Musicam and Dolby AC3. The device is expected to cost $50 or less, depending on configuration and quantity. LSI Logic Corp, Milpitas, CA. (408) 433-8000.

State-machine tool generates 32-bit object-oriented code. A PC-based, graphical state-machine design tool, BetterState Pro V3.5 supports not only state charts, but also 32-bit object-oriented code generation. Other features of V3.5 include a scheme for generating coordinator parent classes and enumerated-type state sets for C/C++. The software runs on any PC under Windows 95, NT, or 3.1, with full support for state charts; multirate-firing petri-nets; and a choice of C, C++, Verilog HDL, or VHDL code generators. BetterState Pro V3.5 costs $495. R-Active, Cupertino, CA. (408) 252-2808.

Design software programs analog circuits. Analog Magic 1.2, a Windows-based design program, lets you configure and program working silicon using an intuitive point-and-click interface. The updated program instantly displays the configuration of a programmed device on-screen and performs an integrity test of the EPAC design-system setup. The EPAC development starter kit, including Analog Magic 1.2, two IMP50E10 EPAC general-purpose signal-conditioning circuits, and a programming board, costs $395. Imp Inc, San Jose, CA. (408) 432-9100.

Verification software performs cycle-based simulation. A Verilog HDL-based digital-logic simulator increases gate-level performance using cycle-based techniques without design or methodology restrictions. Called "vls," the simulator provides cycle-based verification and timing simulation for million-gate designs of embedded cores and memories, complex clocks, and a mix of synchronous and asynchronous circuitry. Prices for the vls logic simulator, which runs on Unix-based platforms, start at $25,000. Pendulum Design Inc, Waltham, MA. (617) 487-9959.

Design program automates cell migration. Part of the Masters Library development tools family, MasterPort is a stand-alone tool that lets you automatically migrate existing cell libraries from one process technology to another. MasterPort imports GDSII and Spice data for existing cell libraries and automatically outputs GDSII and annotated Spice data for the same library using a different process. The library’s main component is the GafEdit interface, a graphical front end for automatic constraint generation. MasterPort runs on HP and Sun workstations and costs $150,000. Cascade Design Automation, Bellevue, WA. (206) 643-0200.