Out in Front: March 14, 1996
The PLD is available in three versions, depending on how you use the embedded RAM. One version provides a single-port RAM with an organization of 512×9 or 256×18 bits. A second version provides dual-port RAM with the same organization choices and with arbitration logic to resolve access conflicts. A third version lets you use the RAM as a 512×9- or 256×18-bit FIFO buffer. The FIFO version provides full and empty flags plus programmable almost-full and -empty flags to indicate any level you choose. Memory access time is 15 nsec.
The register/counter module provides eight 16-bit registers that you can cascade and use in several modes. The module can implement a register file, loadable up/down counters, up/down timers, and parallel-to-serial or serial-to-parallel shift registers. The timers can use preset values written into EEPROM, or you can load the values each time you use the counter. You can implement multiple functions in the module at once. For example, you can simultaneously implement four 16-bit counters and four 16-bit register files. The register-counter module accommodates count and shift frequencies as high as 125 MHz.
The in-system programmable device uses EEPROM technology and offers dedicated IEEE 1149.1 JTAG (Joint Test Action Group)-compatible testability. It comes in a 208-pin MQFP with 157 user pins. Samples are available now, and Lattice has scheduled production for the second quarter. The device costs $225 (1000)
by Doug Conner
Lattice Semiconductor Corp, Hillsboro, OR. (503) 681-0118