Out in Front: March 14, 1996

Synopsys has added behavioral retiming (BRT) to the Behavioral Compiler. You use Behavioral Compiler with a VHDL or Verilog behavioral description to evaluate design architectural alternatives and create a gate- or register-transfer-level (RTL) design description. BRT moves registers in a design to optimal locations without affecting the associated control logic. You use BRT on RTL designs from Behavioral Compiler that the tool has synthesized to the gate level. BRT performs sequential optimization on the design's registers. By moving registers across combinatorial logic and the design's hierarchical boundaries, BRT produces a new gate-level design with the fewest registers needed to meet performance specifications. Synopsys claims an average timing improvement of 15% on customer benchmarks using as many as 30,000 gates, with an average area penalty of 5%.

You use BRT only for statically timed, single-clock designs that do not use gated clocks. Examples include finite state-machine controllers, datapaths and mixed-control-data-path designs. You can also use BRT on multiclock designs if you can split the design into single-clock portions that you optimize separately. According to Synopsys, Behavioral Compiler with BRT can process 30,000 logic gates in eight hours, with runtime proportional to the number of gates. BRT is available now in Behavioral Compiler, which runs on Digital Equipment, Hewlett-Packard, IBM, and Sun Unix-based workstations. Behavioral Compiler, with Synopsys' most advanced behavioral, RTL, and logic-synthesis capabilities, costs $155,000.
—by Jim Lipman

Synopsys, Mountain View, CA. (415) 962-5000