Out in Front: March 14, 1996

A stereo digital-audio-playback IC, Analog Devices' AD1859, includes a digital PLL that allows the master clock to be asynchronous to the inputs and that rejects jitter on the sample clock. As a result, you do not have to provide a multiple-rate external clock generator to handle various input sampling rates, such as 44.1k and 48k samples/sec. The PLL-based clock locks onto a new sample rate within 100 msec and attenuates those jitter components that are more than 15 Hz away from the sampling frequency by 6 dB per octave.

The 16/18-bit resolution IC includes a variable-rate digital interpolation filter, a sigma-delta modulator with dither, a D/A converter, analog filters, analog output-drive circuitry, and attenuator and mute functions. The modulator uses a multibit architecture that reduces out-of-band noise that normally must be filtered to avoid subsequent "beating" with other signals in the system. You program the 5V, 28-lead device (SSOP and SOIC packages) through a serial-peripheral-interface-compatible port; it costs $4.90 (1000).
—by Bill Schweber

Analog Devices Inc, Norwood, MA. (617) 937-1428