Design Feature: March 28, 1996

If you view reconfigurable FPGAs only as static-logic devices that accommodate design changes during prototyping and as occasional field upgrades, you are missing the latest frontier in digital design. The ability of infinitely reprogrammable FPGAs to dynamically redefine hardware provides performance improvements you can't afford to ignore.

Reconfigurable logic is not so much a new product as it is a new way thinking. Although SRAM-based FPGAs have been available for years, new devices are offering greater performance. Depending on the device used, you can reprogram an SRAM-based FPGA from several times a second to more than a thousand times a second. Despite the device's flexibility, most designers use the reprogrammable capability as a development aid to debug and refine designs and, occasionally, for field upgrades.

In the context of this article, reconfigurable logic refers to infinitely reprogrammable logic devices. Reconfigurable logic differs from reprogrammable logic, which includes devices with a limited reprogramming life, such as EPROM, EEPROM, or flash-technology-based devices. Reprogrammable devices offer many of reconfigurable logic's features, especially ease of development and field upgrades. These devices aren't suitable for dynamic-logic applications, however.

Many designers haven't used the inherent flexibility of reconfigurable logic devices. Engineers have static-logic-design education and experience. Reusing logic implies sharing resources and multiplexing functions. Two functions might use a counter at different times, provided that the functions don't simultaneously need the counter. This practice reflects the static-logic way to view the world.

The dynamic-logic view of the world offers more flexibility. Logic cells acting as counter can become an ALU. Later, the logic cells might perform video edge detection or act as a digital filter. You can think of reconfigurable FPGAs as uncommitted gates. You can use a gate for only one function at a time. When you no longer need that function for a period of time, you have free gates for performing other functions.

Cache logic

Atmel, a manufacturer of SRAM-based FPGAs, promotes the concept of cache logic, which is analogous to cache memory. You load the active logic needed from inexpensive memory. Logic that is temporarily not in use is overwritten with the logic the system currently needs. Dynamic logic performs the same function as static logic—with fewer total gates, which may also result in lower power consumption for a system.

The AT6000 family of FPGAs from Atmel has several features that suit cache logic. First, the devices are partially reconfigurable. You don't have to program the entire device when you want to change a function. You just program the logic elements you wish to change. You can partially reprogram the device at 100 nsec/cell, or you can reprogram an entire 10,000-gate device in 646 µsec.

Even when you are reprogramming the device, the FPGA doesn't have to sit idle. The device lets you reprogram inactive areas on the FPGA as active areas continue to operate. Clocks can continue cycling, and registers don't lose their contents. Devices that allow only full reconfiguration typically can't operate during reconfiguration. In addition, these devices lose register contents during reconfiguration.

Reconfigurable coprocessing

One way to use cache logic is in a coprocessor mode. You use a CPU to perform functions, and you program the reconfigurable coprocessor to perform complex instructions (for which the CPU is inefficient). Reconfigurable logic is capable of implementing large pipelined processing operations or highly parallel operations (or both).

Xilinx designed its XC6200 family specifically for coprocessing applications. Members of the XC6200 family have a built-in µP interface that you can program to accommodate 8-, 16-, or 32-bit data. In addition, a high-speed interface provides instant read/write access to all internal registers of the FPGA.

The first member of the XC6200 family, the XC6216, will be available in the second quarter. The device has 4096 cells arranged in a uniform 64-row × 64-column structure. Each cell has a register and performs all types of two-input logic functions. Alternatively, you can use a logic cell as 2 bytes of synchronous RAM. The company estimates the gate utilization of each cell at four to six gates for a total of 16,000 to 24,000 gates per device.

The XC6216 suits applications that swap logic into and out of the device. The device has fast partial or full reconfiguration. It is fully configured in 200 µsec or partially reconfigured at 40 nsec/cell. Because the device can quickly read and write the contents of every register, you can save register values when swapping out a function. You can recover register values when you restore the logic configuration. The XC6200 family is similar to Atmel's AT6000 family in that you can simultaneously have reconfiguration on part of the device with a circuit running elsewhere.

A reconfigurable coprocessor works closely with a CPU and typically doesn't need a special operating system (OS). The next step up on the ladder of complexity is a reconfigurable computer, which can work with an extensible instruction set and a variable architecture. The computer is limited only by the flexibility of the reconfigurable devices you use. Reconfigurable computers require a special OS to deal with the potential complexity of such a system. In return for the complexity, you can benefit from the ability to bring in complex instructions, such as for image-processing algorithms, while most often working around a small core of simple instructions.

Reconfigurable computing lets you justify a complex instruction that your design may seldom use. The complex instruction, when used, substantially increases performance. Static-logic designs pay a permanent price in silicon area for implementing complex instructions. Reconfigurable logic requires only inexpensive memory to store the instruction implementation until the instruction is needed.

Reconfigurable logic isn't limited to processor- and coprocessor-type applications. Any application in which you could benefit from having logic implement functions at different times can potentially take advantage of reconfigurable logic.

When considering the use of reconfigurable logic for an application, determine whether you will reconfigure the FPGA once per function or multiple times per function. "Function" refers to some application or task that interfaces either with a human or with another system on human time scales.

With human time scales, changing to a new function typically should be faster than 1/4 sec but probably would seldom benefit from taking less than 10 msec. For example, activating a button to change operations on a test instrument could be considered calling up a new function. Whether the function takes 1 or 100 msec probably wouldn't affect the system's user.

Designs that configure logic only once per function can tolerate relatively long reprogramming times. These devices include those listed in Table 1 as well as some older devices from these manufacturers.

Designs that need to reprogram logic multiple times during a single function are substantially affected by long programming times. If you want to reconfigure an FPGA several hundred times a second, you need a device that reconfigures in a few milliseconds or less. Many of the devices in Table 1 can meet these requirements. Partially reconfigurable devices, such as the Atmel AT6000 family or the Xilinx XC6200 family, not only provide short reconfiguration times, but also allow the rest of the chip to operate productively during partial reconfigurations. Although partially reconfigurable, Lucent Technologies' (formerly, AT&T Microelectronics) 2Cxx FPGA family can't operate during reconfiguration. Devices that can't operate while being reconfigured are completely unproductive during the reconfiguration time.

It is difficult to know how much time you can afford to spend reprogramming. According to Brad Hutchings, an assistant professor of electrical and computer engineering at Brigham Young University (Provo, UT) and a researcher in reconfigurable systems, the time varies widely. For some applications, the efficiency of the device is so high after reconfiguration that even 20% processing and 80% reconfiguring has proven useful. Other applications demand a greater percentage of processing time for efficiency. Hutchings notes that pipelined operations are a case in which full reconfiguration tends to be inefficient. A pipeline keeps the gates working, and reconfiguring interrupts the operation.

In reconfigurable logic, the highest potential performance comes from devices that both reconfigure rapidly and offer partial reconfiguration capability to further enhance speed when making minor changes to the FPGA. This higher potential performance causes greater design complexity, however.

Designs that use only full reconfigurations typically have a more limited set of configurations that you can thoroughly test when designing the system. The use of partial reconfigurations makes possible many combinations of circuits simultaneously present.

When using partial reconfigurations, you may not be able to apply the same physical location every time you implement the logic. Another group of logic functions may be using the location. To avoid the problem, the logic must be relocatable.

For example, Atmel's AT6000 family offers parameterized macro generators that produce hard macros. These macros provide worst-case speed, area, and power consumption and designate the logic cells used. The uniform cell structure in the AT6000 family lets you translate the hard macro or rotate it in 908 increments without changing the macro's performance. The relocation capability lets you move the macro function to an unused group of cells anywhere on the chip.

When partially reconfiguring FPGAs, you must avoid making the transition through potentially destructive configurations in which two outputs are driving the same network. To achieve partial reconfiguration without conflicts, Atmel and Lucent provide software that designates programming sequences to get from one state to the next. Xilinx designed its XC6200 family so that two outputs can't simultaneously drive the same network.

Connecting it all

Reconfigurable logic is not just a reconfigurable sea of gates. Commercially available RAM-based FPGAs don't offer unlimited connectivity. Connectivity involves whether you can connect the logic cells the way you want after you have found space for all logic functions. Furthermore, the connectivity issue can be split into an on-chip problem and a separate off-chip problem when using two or more reconfigurable devices.

FPGA designers have to make difficult choices between routing resources and logic. RAM-based FPGAs for a given silicon area have to trade usable logic gates for routing resources. More routing resources mean fewer usable logic gates, which, in turn, drive up the cost per gate. The end result of this trade-off is that designers of SRAM-based FPGAs try to design in adequate routing resources without leaving excess routing resources, which the designers could use more profitably as gates.

When trying to route a design that has filled up most or all of the logic cells, you may run into routing problems. In the worst case, you may find that the design simply does not route. A more likely scenario is that the design routes, but a certain number of paths are too slow. If you've used an FPGA that is too slow for your application, even when optimally routed, you have to use a faster device. Often, overworking the routing resources and forcing some networks to use long, slow routing paths cause speed problems on a few of the networks. To solve this problem, you need to use automatic or, in some cases, manual methods to force less critical networks onto the slower paths and use the fastest paths for the signals that need them.

Altera's Flex 8000 and 10K devices have an interconnect structure that offers more predictable timing before place and route than other devices. In fact, the company refers to its devices as "complex PLDs," because they have a routing structure with fixed delays. This structure relates more to PLDs than to the segmented routing resources of most FPGAs. You can still run out of routing resources, but you have to go out of your way to create slow routing paths.

If your design requires more than one FPGA, connectivity between the devices becomes an issue. Reconfigurable logic may require more than just reconnecting gates at a low level. The system may require altering the architecture of the design at a higher level. Larger designs typically place more demands on data flow and bus throughput to handle greater data rates.

For example, one application might favor linking devices in a linear pipeline arrangement, in which data is processed on one device and passed down to other devices for further processing. Another application might require highly parallel operations in which data is distributed among many identical processing elements. In addition, one application may favor localized memory, and another may favor global memory.

Reconfigurable logic scores high marks for allowing reconfigurable architectures. Compared with static-logic design, in which you have to select one type of bus and stick with it, reconfigurable logic offers a world of flexibility. You can actually use different busing schemes at different times for operations.

Reconfigurable logic does have limitations when you use multiple reconfigurable chips, however. Packaging technology limits the number of pins to a few hundred, yet these devices may have thousands of logic cells. The complete connectivity of a crosspoint-switch model is not possible on these larger designs, even if you could get enough I/O pins.One approach to the multichip interconnect problem is to keep a large, reconfigurable bus connecting the reconfigurable logic devices. Rather than committing to one busing architecture, you can use a reconfigurable bus that allows multiple bus types. When a bus interconnect exclusively uses reconfigurable devices, you can redefine the networks on an individual basis, using various busing schemes and connecting chips at different times.

To improve connectivity, especially in large designs, you can use field-programmable interconnect devices, such as those from I-Cube. The crosspoint switches let you quickly reconfigure connections, providing reconfigurability in your off-chip connections consistent with the on-chip flexibility of reconfigurable logic.

Although connectivity can be a problem for reconfigurable logic designs, especially large ones requiring arrays of FPGAs, careful analysis and design provide workable solutions. Cost, however, is a much more troublesome problem for reconfigurable logic and FPGAs.

An FPGA requires significantly more silicon area than does a mask-programmed gate array with the same number of gates. Static-logic designs are difficult to justify on FPGAs, except in low volumes in which NRE charges and low-volume manufacturing drive up the cost of mask-programmed devices to comparable levels. If you compare the device cost of FPGAs to that of mask-programmed devices, the crossover point is typically around a few thousand devices. Simple math might lead you to believe that FPGAs are good for prototyping and for extremely low production volumes, but the device will never be a high-volume product.

The real world tells a different story. Xilinx ranks as the 10th largest ASIC supplier worldwide, with $355 million in revenues for the fiscal year ending March 31, 1995. Xilinx's FPGA competitors are also growing rapidly. FPGAs have proven to be an economically viable method for implementing logic for a small, but fast-growing, part of the digital market. Some of the reasons for the popularity of FPGAs include short development time, low development cost, and the ability to respond quickly to market changes whether from customer needs or from compatibility with evolving standards. Designers find that just about every design keeps evolving, so the decision as to when to cast a design in silicon is a tough one to make.

The use of FPGAs in reconfigurable logic designs not only capitalizes on an FPGA's strong points, but also leverages the gates to improve the economic viability of FPGAs. The usable gates of a device might be multiplied by two, 10, or more, depending on how you take advantage of reconfiguration in your design. The end results are that the cost per gate drops and that reconfigurable logic can compete in a wider range of applications.

The other weak point for FPGAs is speed. FPGAs can't offer clock rates quite as high as mask-programmed devices. Furthermore, interconnect problems on some designs cause clock rates to drop further. Although there are some applications in which FPGAs are just too slow, the devices are fast enough for many applications. Nailing down specific clock speeds is difficult, because the speeds are so application-dependent. Applications that run on a single FPGA might typically run from 15 to 100 MHz. Designs spread across multiple FPGAs may suffer further speed reductions.

Using reconfigurable logic at maximum speed may require you to use pipelined-design and parallel-processing techniques at lower clock speeds than you would in a mask-programmed device. For very high-speed serial data rates, you may need to perform off-chip conversion, so that you can use lower speed parallel data paths on the FPGA.

If you think of reconfigurable logic as competing for speed with mask-programmed devices, the technique comes up a little short. Instead, consider the ability of reconfigurable logic to accelerate algorithms that would otherwise have to be performed in software. In this comparison, reconfigurable logic commonly provides more than an order-of-magnitude speed improvement.

For years, the trade-off has always been that software has the best flexibility and lowest cost for executing algorithms, especially complex algorithms, and hardware offers the greatest speed, but at the greatest cost. Hardware design also takes more time to design and time to implement. Reconfigurable logic changes the landscape. Although reconfigurable logic is more expensive than mask-programmed gate arrays on a gate-per-gate basis, the ability of reconfigurable logic to reuse the gates alters the cost equation. Designers need to re-examine what should be done in software and in hardware—reconfigurable hardware.

References

1. Athanas, Peter, and Kenneth Pocek, Editors, IEEE Symposium on FPGAs for Custom Computing Machines, 1995.

2. Schewel, John, Editor, SPIE Proceedings on Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, 1995, Vol 2607.

3. http://www.reconfig.com on the Internet.