Design Ideas: March 28, 1996
V Krishnamurthy,
Naval Physical and Oceanographic Laboratory, Kochi, India
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The modulator in Figure 2a uses the DATA_STROBE signal to load the N-bit
output word into a down-counter. DATA_STROBE also clears the D flip-flop making the Q
output low. When the counter counts down to its terminal value, the RCO signal clocks the
flip-flop, which makes the Q output go high. Thus, based on the output data, the circuit
produces a variable-width pulse at the Q output. The circuit solves the necessity of a
common clock in a pulse-width-coded communication by OR-ing the Q output with the clock
signal. The OR gate's output, PWMN, and DATA_STROBE comprise the two output lines.
This circuit needs only half the number of gates of a two-counter PWM circuit. Although single-counter PWM circuits need an up/down-counter, this design needs only a down-counter. This circuit also works correctly for the terminal values 0 and F, which are generally a problem with simple, single-counter designs.
The simple demodulator circuit in Figure 2b comprises merely an up-counter chain that PWMN clocks and DATA_STROBE clears. Data is available at the output of this counter at the falling edge of the next DATA_STROBE. The actual circuits in Figure 2 have been designed and tested, without loss of generality for N=4 on the Altera Max+Plus2 system running on a 486 PC. (Click here to download DI_SIG #1847.)
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