Design Ideas: March 28, 1996

The ADSP2100A executes all instructions in a single, 80-nsec clock cycle; so to interface the 82530, you need a facility (wait states) to extend the processor cycle for all 82530 accesses to the processor. Also, the 82530 requires that data to the SCC be valid while the write signal (WR) to the SCC chip goes low. However, data on the ADSP2100A data bus is not valid on the falling edge of the write signal (DMWR) to the ADSP2100A. Another problem with the 82530 is that it has no explicit hardware reset input. To reset the device, you must simultaneously take its chip-select, write, and read signals low.

A minimum of glue logic solves the above problems (Figure 1). You extend the ADSP2100A's cycles by making use of the chip's data-memory acknowledge (DMACK) input. The ADSP2100A checks the status of the DMACK signal near the end of each data-memory access cycle. If DMACK is low, the DSP chip extends the current cycle by another full cycle. This extension recurs until the DMACK signal samples high, for the completion of the cycle. The 82530 is available in different speed versions; the 4-MHz version used here requires a minimum of 250 nsec for a read operation. Thus, you must extend the processor cycle by at least four cycles. A wait-state counter implements this extension. You can meet the requirement that data be valid before the WR signal goes low by simply delaying the DMWR output of the ADSP2100A by one processor cycle, then making it go high as soon as DMWR is high.

Figure 2 shows the timing details of the DMWR and WR signals with and without the external logic. A single, industry-standard 22V10 PAL can provide all the glue logic. The Listing gives the PAL design equations for an ABEL compiler. All the flip-flops in the 22V10 are synchronous preset and asynchronous reset types. The DMWR delaying block requires resetting the flip-flop. However, because both the wait-state logic block and the DMWR delaying block use flip-flops in the PAL and the reset line is common to all flip-flops, you cannot reset the flip-flop with the DMWR (as in Figure 1) to ensure that WR goes high as soon as DMWR goes high.

You can overcome this problem by OR-ing the flip-flop output with DMWR. This operation wastes one PAL input pin. Another way is to pull up the flip-flop's output and use DMWR to drive the output-enable pin of the 22V10. This second method saves one PAL input pin. The 82530 is a two-channel SCC; each channel has two types of registers: command and data. By connecting two LSB address bits of the DSP chip directly to the D/C (data or command) and A/D (channel A or B) inputs of the SCC, you can obtain two RS-232C-compatible data channels. The ADSP2100A can program the 82530 for the required baud rate.