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Signals & Noise: April 11, 1996


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Timing-diagram editors offer asynchronous solutions

"To be or not to be asynchronous; that is the question" by Clive "Max" Maxfield (EDN, Dec 7, 1995, pg 157) mentions digital simulators and dynamic timing-analysis tools as being appropriate only for asynchronous design. However, an important class of tools, called "timing-diagram editors," offers a cost-effective alternative for asynchronous design. Timing-diagram editors let the user draw waveforms and set up delays with uncertainty regions between the signal transitions, thus allowing the designer to simultaneously verify minimum/maximum timing.

With a timing diagram, you can easily see the critical paths in an asynchronous design, because the delays show the causal relationships between the signal transistors. This feature explains why designers, even those with access to powerful digital simulators, still hand-draw timing diagrams. Designers can use the WaveFormer from SynaptiCad and dV/dt from Engineerium as timing-diagram editors to design asynchronous circuits. These tools sell for less than $1000 and offer capabilities lacking in more expensive digital simulators.

Dan Notestein
SynaptiCad
Blacksburg, VA<\i>


Sources for test design

"Design for test—or else..." (EDN, Jan 18, 1996, pg 11) really hits home. I work for a company that builds complicated scientific equipment for space.

Our designers are currently doing almost iterative design on 164-pin FPGAs at $400 a pop. We can verify only so much when the software finds an error. We then have to update the FPGA. Invariably, this goes on for several revisions. There is a problem in designing something to be testable. It seems that the key signal you want to debug or get to is not easily accessible. Managers expect that the circuit will work the first time. It's tough in the space industry, because we don't use sockets for our ICs.

If you have any references for designing for test, I would greatly appreciate it.

Robert Deschambault
Com Dev Ltd
Cambridge, ON, Canada

(Senior Technical Editor Dan Strassberg replies: Dmitrii Loukianov's article, "You need little more than a PC to test and program IEEE-1149.1-compliant ICs" (EDN, Nov 9, 1995, pg 171), provides some ideas on features that ASICs should include to assure testability. A good book on designing for testability (though primarily for board designers) is Building a Successful Board-Test Strategy by Stephen F Scheiber (Butterworth-Heinemann 1995; ISBN: 0-7506-9432-7).


Not-so-smart cards

"Smart cards—trained for security" (EDN, Nov 23, 1995, pg 34) was timely and informative for those of us planning and designing conditional access systems and renewable security methods for interactive broadband services. Before falling in love with smart cards, however, I suggest that we look at European Scrambling Systems, the Black Book by John McCormac ($60; Baylin Publications, (800) 483-2423; ISBN 1-873556-03-9).

According to McCormac, the VideoCrypt encryption system used by BSkyB has a chilling record of devastating and costly security failures. The European VideoCrypt system, using the issue 07 card, was hacked in 1984, but articles about the break did not appear until 1989. The card's source code was distributed on the Internet and freely accessible. As a result, an entire pirate-card industry was created that, unfortunately, still exists today. It is hard to stop an insidious enterprise.

The new cards appear advanced. But, large numbers of subscribers will create an enormous incentive to attack the heart of the authentication and authorization access-control methods. We should temper our hunger for functional elegance with reality: No single conditional-access method (that is economical) can guarantee invulnerability. The value of access control can actually exceed that of the service it protects. We must balance the cost of access-control systems with access convenience and defense effectiveness.

Victor A Nowakowski,
Ameritech
Chicago, IL



Corrections and updates

In "Keep regulators in the safe zone" (EDN, Oct 26, 1995, pg 137), Equation 2 and related calculations should have reflected minimal, not nominal, values.

In the "Out in Front" section in the Dec 7, 1995, issue, Radisys Corp's R380EX system-controller chip can control 64 Mbytes of DRAM rather than the 64 bytes mentioned. Also, the chip comes in a 208-pin PQFP and not in the 20-pin PQFP mentioned.

Also, due to an editing error, we listed an incorrect spec in "PC graphics struggle to incorporate 3-D" (March 1, 1996, pg 61). Tests on Pentium show that it can handle geometry calculations at 1000 triangles/MHz of clock speed—not the 100,000 the article lists.

We listed the incorrect phone number for Silicon Sound's Runabout Robot (EDN, Tech Toys, Dec 7, 1995, pg 112). The correct phone number is (818) 996-5073.


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