Out in Front: April 11, 1996
Last year's debut of Intel's 8xC251 proves that there's still life in the 8051 architecture that the company introduced more than 15 years ago. The 8xC251, which handles up to 24-bit addressing and contains a register-based CPU, delivers as much as 15 times the performance of the earlier 80C51, according to Intel. Now, the company is offering the 80C151, which should hit a performance and price point between those of the 80C51 and 80C251. The 80C151 provides as much as five times the performance of and is drop-in-compatible with the 80C51. The new device uses the 80C51 instruction set and maintains binary-code compatibility with the earlier product.
Like the 80C251, the 80C151 replaces the 80C51's sequential instruction execution unit with a pipelined structure that operates as fast as 16 MHz. This approach allows the new architecture to complete instructions in a minimum of two clocks per instruction vs the 80C51's 12. Also like the 80C251, the 80C151 includes a 16-bit internal code bus, page mode, an external wait-state generator, a programmable counter array, a hardware watchdog timer, and three timer/counters. Page mode allows users to accelerate external instruction fetches.
The 80C151 is available in ROMless, one-time-programmable, or ROM versions in 40-lead PDIP or 44-lead PLCC packages. ROM version prices are $5 or $6.50 with 8 or 16 kbytes of memory, respectively. Dallas Semiconductor and Philips Semiconductors also offer performance-enhanced versions of the 8051.
—by Markus Levy